Method of driving transistor
View Patent ↗A shift register has multiple stages each of which includes a pull-up part to generate a current gate line driving signal having a first state in response to a first control signal and a clock signal, a pull-down part to generate the current gate line driving signal having a second state in response to a second control signal, a pull-up driver to generate the first control signal to control the pull-up part in response to a previous gate line driving signal provided from a previous stage, a following gate line driving signal provided from a following stage, and an input voltage signal externally provided, and a pull-down driver to generate the second control signal to control the pull-down part in response to a third control signal provided from the pull-up driver and the input voltage signal, in which the second control signal swings between first and second voltage levels in association with the input voltage signal that swings between predetermined voltage levels.
1. A method of driving an amorphous silicon thin film transistor having gate, drain and source electrodes, the method comprising:
applying a first voltage signal to the drain electrode of the amorphous silicon thin film transistor;
applying a second voltage signal to the source electrode; and
applying a third voltage signal to the gate electrode to control an electrical conduction path between the drain and source electrodes, wherein the third voltage signal swings between a minimum voltage level and a maximum voltage level,
when the voltage level of the third voltage signal is the minimum voltage level, the voltage difference of the third voltage signal and second voltage signal exceeds a normal threshold voltage level of the amorphous silicon thin film transistor, and
when the voltage level of the third voltage signal is the maximum voltage level, the voltage difference of the third voltage signal and second voltage signal exceeds a threshold voltage level of the amorphous silicon thin film transistor which is increased due to deterioration of the amorphous silicon thin film transistor.
2. The method of claim 1 , wherein the voltage difference of the third voltage signal and second voltage signal has an amplitude larger than two times the normal threshold voltage of the amorphous silicon thin film transistor.
3. The method of claim 1 , wherein the third voltage signal has an amplitude larger than seven times the normal threshold voltage of the amorphous silicon thin film transistor.