Circuit emulation and debugging method
A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals.
1. A method for predicting time-varying behavior of signals of a circuit that are referenced by a register transfer level (RTL) description of the circuit, wherein the signals comprise internal signals and other signals, wherein the other signals consist of all circuit input and output signals, and all input and output signals of memory devices described as being included in the circuit, and wherein the RTL description of the circuit indicates that the circuit derives the internal signals from the other signals, the method comprising the steps of:
a. processing the RTL description of the circuit to determine logical relationships between the internal signals and the other signals and to identify the memory devices;
b. processing the RTL description of the circuit by a computer-based synthesizer to synthesize a first gate level description of the circuit including the memory devices identified at step a, wherein the first gate level description references the other signals but omits reference to the internal signals;
c. processing the first gate level description of the circuit to program a circuit verification system to produce waveform data representing time-varying behavior of the other signals of the circuit; and
d. processing the waveform data generated by the circuit verification system to produce additional waveform data representing time-varying behavior of the internal signals referenced by the RTL description of the circuit in accordance with the determined logical relationships between the internal signals and the other signals.
2. The method in accordance with claim 1 further comprising the step of:
e. processing the additional waveform data to produce displays representing the time-varying behavior of the internal signals.
3. The method in accordance with claim 1 wherein step a comprises the substeps of:
a1. processing the RTL description of the circuit to synthesize a second gate level description of the circuit referencing the other signals, the internal signals referenced by the RTL description of the circuit and the memory devices; and
a2. processing the second gate level description of the circuit to determine logical relationships between the internal signals and the other signals and to identify the memory devices.
4. The method in accordance with claim 1 wherein the circuit verification system comprises a circuit emulator.
5. The method in accordance with claim 1 wherein the circuit verification system comprises a circuit simulator.
6. The method in accordance with claim 1 wherein step a comprises generating a separate Boolean equation corresponding to each internal signal describing a state of the equation's corresponding internal signal as a function of a state of at least one of the other signals.
7. The method in accordance with claim 1 wherein the memory devices comprise clocked registers.
8. The method in accordance with claim 7 wherein the memory devices further comprise at least one addressable memory.
9. A method for predicting behavior of internal signals of a circuit described by a register transfer level (RTL) description of a circuit design comprising the steps of:
a. processing the RTL description to determine for each internal signal of the circuit described by the RTL description, a logical relationship between the internal signal and other signals of the circuit described by the RTL description, wherein the internal signals comprise all signals other than input and output signals of the circuit and other than input and output signals of memory devices included in the circuit described by the RTL description;
b. synthesizing an optimized gate level description of the circuit design from the RTL description, wherein the circuit described by the optimized gate level description omits at least one of the internal signals of the circuit described by the RTL description but includes all of the other signals of the circuit described by the RTL description;
c. emulating the circuit described by the optimized gate level description using a circuit emulator to produce waveform data representing behavior of the other signals; and
d. processing the waveform data describing behavior of the other signals to produce additional waveform data representing behavior of the at least one omitted internal signal in accordance with the determined logical relationships between the at least one omitted internal signal and the other signals.
10. The method in accordance with claim 9 further comprising the step of:
e. processing the additional waveform data to produce displays representing the time-varying behavior of said at least one omitted internal signal.
11. The method in accordance with claim 9 wherein step b comprises the substeps of:
b1. processing the RTL description to synthesize a non-optimized gate level description of the circuit design referencing all of the internal and other signals referenced by the RTL description; and
b2. processing the non-optimized gate level description to determine the logical relationships between the internal signals and the other signals referenced by the RTL description.
12. The method in accordance with claim 9 wherein step b comprises generating a separate Boolean equation corresponding to each internal signal describing a state of the equation's corresponding internal signal as a function of a state of at least one of the other signals.
13. A method for predicting behavior of internal signals of a circuit described by a register transfer level (RTL) description of a circuit design comprising the steps of:
a. processing the RTL description to determine for each internal signal of the circuit described by the RTL description, a logical relationship between the internal signal and other signals of the circuit described by the RTL description, wherein the internal signals comprise all signals other than input and output signals of the circuit and other than input and output signals of memory devices included in the circuit described by the RTL description;
b. synthesizing an optimized gate level description of the circuit design for the circuit from the RTL description by a computer-based synthesizer, wherein the circuit described by the optimized gate level description omits at least one of the internal signals of the circuit described by the RTL description but includes all of the other signals of the circuit described by the RTL description;
c. simulating the circuit described by the optimized gate level description to produce waveform data representing behavior of the other signals; and
d. processing the waveform data describing behavior of the other signals to produce additional waveform data representing predicted behavior of the at least one omitted internal signal in accordance with the determined logical relationships between the at least one omitted internal signal and the other signals.
14. The method in accordance with claim 13 further comprising the step of:
e. processing the additional waveform data to produce displays representing the time-varying behavior of the internal signals.
15. The method in accordance with claim 13 wherein step b comprises the substeps of:
b1. processing the RTL description of the circuit design to synthesize a non-optimized gate level description of the circuit design referencing all of the internal and other signals referenced by the RTL description of the circuit design; and
b2. processing the non-optimized gate level description of the circuit design to determine the logical relationships between the internal signals and the other signals referenced by the RTL description of the circuit design.
16. The method in accordance with claim 13 wherein step b comprises generating a separate Boolean equation corresponding to each internal signal describing a state of the equation's corresponding internal signal as a function of a state of at least one of the other signals.