Granted Patent B2

US 7,925,798 · App. 11/698,670 · Granted Apr 12, 2011

Abstract

Claims (59)

1. A device comprising:

a processor implemented on a chip;

an on-chip internal segment memory accessible by the protocol processor;

an off-chip external segment memory;

a data transfer channel between the internal segment memory and the external segment memory;

an off-chip external table memory configured for segment allocation management of the external segment memory;

an on-chip internal table memory configured for segment allocation management of the external segment memory;

an address transfer channel between the external table memory and the internal table memory;

an address transfer management unit operative to transfer segment addresses of memory segments of the external segment memory from the external table memory into the internal table memory and/or to transfer segment addresses of memory segments of the external segment memory from the internal table memory into the external table memory;

an input data processing unit for mapping incoming PDUs into an internal data format comprising a first data segment and a second data segment; and

an output data processing unit for reassembling first and second data segments of the internal data format into PDUs to be output;

wherein the address transfer management unit is configured to:

monitor the fill level of the internal table memory; and

to initiate a transfer of one or more addresses from the external table memory to the internal table memory if the fill level is lower than a lower threshold value and/or

to initiate a transfer of one or more addresses from the internal table memory to the external table memory if the fill level is higher than an upper threshold value, wherein the upper threshold value is greater than the lower threshold value.

2. The device according to claim 1 , wherein the processor is a protocol processor.

3. The device according to claim 1 , wherein the internal table memory comprises a list of free memory segments of the external segment memory.

4. The device according to claim 3 , wherein the external table memory comprises a list of additional free memory segments of the external segment memory which are not contained in the list hold in the internal table memory.

5. The device according to claim 3 , wherein the internal table memory comprises a number of first storage units for storing addresses of the external segment memory, the number of first storage units being smaller than the number of segments of the external segment memory.

6. The device according to claim 5 , wherein the internal table memory further comprises a number of second storage units for storing addresses of the internal table memory, wherein each second storage unit is associated with a first storage unit.

7. The device according to claim 5 , wherein the external segment memory comprises 2 k segments and the internal table memory comprises 2 i first storage units, with i<k.

8. The device according to claim 1 , wherein the external segment memory comprises first and second memory segments, the first and second memory segments are different in size.

9. The device according to claim 8 , wherein the on-chip internal table memory is configured for segment allocation of the first and second memory segments of the external segment memory.

10. The device according to claim 9 , wherein the address transfer management unit is configured

to monitor a first fill level of the internal table memory in respect of first memory segments and a second fill level of the internal table memory in respect of second memory segments and

to initiate a transfer of one or more addresses of first or second memory segments from the external table memory to the internal table memory if the first or second fill level is lower than a lower threshold value, respectively, and/or

to initiate a transfer of one or more addresses of first or second memory segments from the internal table memory to the external table memory if the first or second fill level is higher than an upper threshold value, respectively, wherein the upper threshold value is greater than the lower threshold value, respectively.

11. A method for storing PDU data intended for protocol processing by a protocol processor implemented on a chip, comprising:

mapping incoming PDU data into an internal data format comprising data segments;

allocating memory segments in an off-chip external memory for storing the data segments by accessing a list recording addresses of free memory segments of the external segment memory, the list is maintained in an on-chip internal table memory, wherein an off-chip external table memory comprises a list of additional free memory segments of the external segment memory which are not contained in the list held in the internal table memory;

monitoring a fill level of the internal table memory and

initiating a transfer of one or more addresses from the external table memory to the internal table memory if the fill level is lower than a lower threshold value; and/or

initiating a transfer of one or more addresses from the internal table memory to the external table memory if the fill level is higher than an upper threshold value, wherein the upper threshold value is greater than the lower threshold value.

12. The method according to claim 11 , further comprising:

mapping incoming PDU data into an internal data format comprising a first data segment and a second data segment; and

allocating first and second memory segments of different sizes in the external segment memory for storing the first and second data segments by accessing a first list recording addresses of free first memory segments of the external segment memory and by accessing a second list recording addresses of free second memory segments of the external segment memory.

13. The method according to claim 12 , wherein the first list and the second list are commonly held in the internal table memory.

14. The method according to claim 12 , wherein

monitoring a first fill level of the internal table memory in respect of first memory segments and a second fill level of the internal table memory in respect of second memory segments, and

initiating a transfer of one or more addresses of first or second segments from the external table memory to the internal table memory if the first or second fill level is lower than a lower threshold value, respectively, and/or

initiating a transfer of one or more addresses of first or second segments from the internal table memory to the external table memory if the first or second fill level is higher than an upper threshold value, respectively, wherein the upper threshold values are greater than the lower threshold values, respectively.

15. A data packet processing device, comprising:

a protocol processor implemented on a chip;

an on-chip internal segment memory accessible by the processor;

an off-chip external segment memory not directly accessible by the processor;

an input data processing unit coupled to said off-chip external memory configured to map an incoming PDU into an internal data format comprising a first data segment to be subjected to protocol processing and one or more second data segments not to be subjected to protocol processing; and

a data transfer channel between the internal segment memory and the external segment memory;

wherein the external segment memory comprises first and second memory segments, the first and second memory segments being different in size;

wherein the data transfer channel is configured to transfer data stored in the first memory segments of the external segment memory to the internal segment memory whereby data stored in the second memory segments is not transferred through the data transfer channel to the internal segment memory;

wherein the protocol processor is configured to process the first data segment from internal memory and return through the data transfer channel the processed first data segment to the external segment memory; and

an output data processing unit configured to reassemble the PDU from processed first data segment and unprocessed segment data segment and transform internal data format into the data format used by the PDU.

16. A method for data processing, comprising:

mapping incoming PDU data into an internal data format comprising a first data segment to be subjected to protocol processing and one or more second data segments not to be subjected to protocol processing;

storing first and second data segments in an off-chip external segment memory not directly accessible by a protocol processor, wherein the external segment memory comprises first and second memory segments, the first and second memory segments being different in size;

transferring the first data segment from off-chip external segment memory through a data transfer channel to an on-chip internal segment memory accessible by the protocol processor, whereby data stored in the second memory segments is not transferred thorugh the data transfer channel to the on-chip internal segment memory;

processing the first data segment from internal memory by the protocol processor;

returning through the data transfer channel the processed first data segment to the external segment memory;

reassembling the PDU from processed first data segment and unprocessed second data segments; and

transforming internal data format into the data format used by the PDU.

Assignments (10)