Voltage level shift circuit and semiconductor integrated circuit

1. A voltage level shift circuit, comprising:

at least two source follower circuits for shifting a level of a direct current voltage of an input signal and outputting the direct current voltage of the input signal;

cascode circuits each connected between each of the source follower circuits and a power supply, for applying a bias voltage of a power supply voltage to the source follower circuits, wherein each of the cascode circuits is formed of at least one N-channel depletion type MOS transistor;

means for controlling the bias voltage of each of the cascode circuits by a bias voltage signal from a source follower circuit which is unconnected to the cascode circuit in series; and

means for outputting the signal the level of which is shifted by the source follower circuits as an input signal of a differential amplifier circuit.

2. A voltage level shift circuit according to claim 1 , wherein:

each of the source follower circuits comprises:

a P-channel enhancement type MOS transistor; and

an N-channel depletion type MOS transistor serially connected to the P-channel enhancement type MOS transistor to be a constant current load of the P-channel enhancement type MOS transistor; and

each of the source follower circuits is formed on a P-type substrate.

3. A voltage level shift circuit according to claim 1 , further comprising:

a first source follower circuit including a first voltage signal input terminal, a first voltage signal output terminal, and a first bias voltage output terminal;

a second source follower circuit including a second voltage signal input terminal, a second voltage signal output terminal, and a second bias voltage output terminal;

a first cascode circuit serially connected to the first source follower circuit;

a second cascode circuit serially connected to the second source follower circuit;

means for controlling a bias voltage of the second cascode circuit based on a voltage outputted from the first bias voltage output terminal; and

means for controlling a bias voltage of the first cascode circuit based on a voltage outputted from the second bias voltage output terminal.

4. A voltage level shift circuit according to claim 3 , further comprising:

a first source follower circuit including:

a first P-channel enhancement type MOS transistor, a gate terminal of which is connected to a first voltage signal input terminal and a drain terminal of which is grounded; and

a first N-channel depletion type MOS transistor, a source terminal and a gate terminal of which are connected to a source terminal of the first P-channel enhancement type MOS transistor and to a first voltage signal output terminal and a drain terminal of which is connected to the first bias voltage output terminal;

a second source follower circuit including:

a second P-channel enhancement type MOS transistor, a gate terminal of which is connected to a second voltage signal input terminal and a drain terminal of which is grounded; and

a second N-channel depletion type MOS transistor, a source terminal and a gate terminal of which is connected to a source terminal of the second P-channel enhancement type MOS transistor and to a second voltage signal output terminal and a drain terminal of which is connected to the second bias voltage output terminal;

a first cascode circuit formed of a third N-channel depletion type MOS transistor, a gate terminal of which is connected to the second bias voltage output terminal, a source terminal of which is connected to the drain terminal of the first N-channel depletion type MOS transistor, and a drain terminal of which is fixed to the power supply voltage; and

a second cascode circuit formed of a fourth N-channel depletion type MOS transistor, a gate terminal of which is connected to the first bias voltage output terminal, a source terminal of which is connected to the drain terminal of the second N-channel depletion type MOS transistor, and a drain terminal of which is fixed to the power supply voltage.

5. A voltage level shift circuit according to claim 3 , further comprising:

a first source follower circuit including:

a first P-channel enhancement type MOS transistor, a gate terminal of which is connected to a first voltage signal input terminal and a drain terminal of which is grounded; and

a first N-channel depletion type MOS transistor, a source terminal and a gate terminal of which are connected to a source terminal of the first P-channel enhancement type MOS transistor, to a first voltage signal output terminal, and to the first bias voltage output terminal;

a second source follower circuit including:

a second P-channel enhancement type MOS transistor, a gate terminal of which is connected to a second voltage signal input terminal and a drain terminal of which is grounded; and

a second N-channel depletion type MOS transistor, a source terminal and a gate terminal of which is connected to a source terminal of the second P-channel enhancement type MOS transistor, to a second voltage signal output terminal, and to the second bias voltage output terminal;

a first cascode circuit formed of a third N-channel depletion type MOS transistor, a gate terminal of which is connected to the second bias voltage output terminal, a source terminal of which is connected to the drain terminal of the first N-channel depletion type MOS transistor, and a drain terminal of which is fixed to the power supply voltage; and

a second cascode circuit formed of a fourth N-channel depletion type MOS transistor, a gate terminal of which is connected to the first bias voltage output terminal, a source terminal of which is connected to the drain terminal of the second N-channel depletion type MOS transistor, and a drain terminal of which is fixed to the power supply voltage.

6. A semiconductor integrated circuit, comprising the voltage level shift circuit according to claim 1 .