IP Library Granted Patent US 8,390,634
Granted Patent B2
US 8,390,634 · App. 11/699,996 · Granted Mar 5, 2013

Buffer management in vector graphics hardware

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,390,634
App. No.
11/699,996
Granted
Mar 5, 2013
Kind
B2
Abstract

A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.

Claims (53)

1. A processor unit for processing vector graphics primitives, the processor unit comprising:

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel;

a first internal buffer configured to store at least one indicator bit value for each pixel, wherein said at least one indicator bit indicates status of the counters indicating the state of the fill rule; and

determination logic configured to determine whether or not to retrieve the counter value and whether to retrieve the counter value from an external memory or from a second internal buffer based on the indicator bit values.

2. The processor unit of claim 1 , wherein the processor unit is further configured to clear said external memory by resetting said indicator bit values from said first internal buffer.

3. The processor unit of claim 1 , further comprising:

the second internal buffer configured to store limited values for each counter.

4. The processor unit of claim 3 , wherein the processor unit is further configured to clear said external memory and said second internal buffer by resetting said indicator bit values from said first internal buffer.

5. The processor unit of claim 3 , wherein the indicator bits of the first internal buffer include a value for indicating that a value of the counter has not changed.

6. The processor unit of claim 3 , wherein the indicator bits of the first internal buffer include a value for indicating that a value of the counter has to be retrieved from the external memory.

7. The processor unit of claim 3 , wherein the indicator bits of the first internal buffer include values for indicating a range of the second internal buffer from which the limited value of each counter is retrieved.

8. The processor unit of claim 1 , wherein the processor unit is configured to store counter values for each pixel to be processed in the external memory.

9. The processor unit of claim 1 , wherein the processor unit is configured to store counter values for each pixel to be processed in the second internal buffer.

10. The processor unit of claim 1 , wherein the processor unit is configured to store complete counter values for each sub-pixel having a counter in the external memory.

11. The processor unit of claim 1 , wherein the processor unit further comprises:

the second internal memory configured to store a portion of the complete counter values.

12. The processor unit of claim 11 , wherein the portion is a scan line.

13. The processor unit of claim 11 , wherein the portion is a tile.

14. A processor unit for processing vector graphics primitives, the processor unit comprising:

an internal memory configured to store a portion of vector graphics primitives; and

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel, wherein said value indicates status of the counters indicating the state of the fill rule and indicates whether to retrieve filling information from an external memory;

wherein said portion of vector graphics primitives is a tile corresponding to a portion of the internal memory wherein said vector graphics primitives are stored.

15. A handheld device, comprising:

a display;

an external memory; and

a processing unit operatively coupled to the external memory for processing vector graphics primitives, and including:

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel,

a first internal buffer configured to store at least one indicator bit value for each pixel, wherein said at least one indicator bit indicates status of the counters indicating the state of the fill rule, and

determination logic configured to determine whether or not to retrieve the counter value and whether to retrieve the counter value from the external memory or from a second internal buffer based on the indicator bit values.

16. The handheld device of claim 15 , wherein the handheld device is further configured to clear said external memory by resetting said indicator bit values from said first internal buffer.

17. The handheld device of claim 15 , wherein the handheld device further comprises a bus operatively coupled to the external memory and the processing unit, and wherein said processing unit is configured to receive instructions and data from said bus.

18. The handheld device of claim 15 , wherein the handheld device further comprises a unidirectional bus operatively coupled to the processing unit.

19. The handheld device of claim 15 , wherein the processing unit further comprises:

the second internal buffer configured to store limited values for each counter.

20. The handheld device of claim 19 , wherein the handheld device is further configured to clear said external memory and said second internal buffer by resetting said indicator bit values from said first internal buffer.

21. The handheld device of claim 19 , wherein the indicator bits of the first internal buffer include a value for indicating that a value of the counter has not changed.

22. The handheld device of claim 19 , wherein the indicator bits of the first internal buffer include a value for indicating that a value of the counter has to be retrieved from the external memory.

23. The handheld device of claim 19 , wherein the indicator bits of the first internal buffer include values for indicating a range of the second internal buffer from which the limited value of each counter is retrieved.

24. The handheld device of claim 15 , wherein the external memory is configured to store counter values for each pixel to be processed.

25. The handheld device of claim 15 , wherein the second internal buffer is configured to store counter values for each pixel to be processed.

26. The handheld device of claim 15 , wherein the external memory is configured to store complete counter values for each sub-pixel having a counter.

27. The handheld device of claim 15 , wherein the processor unit further comprises:

the second internal buffer configured to store a portion of the complete counter values.

28. The handheld device of claim 27 , wherein the portion is a scan line.

29. The handheld device of claim 27 , wherein the portion is a tile.

30. An apparatus for processing vector graphics primitives, the apparatus comprising:

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel;

a first internal buffer configured to store at least one indicator bit value for each pixel, wherein said at least one indicator bit indicates status of the counters indicating the state of the fill rule; and

determination logic configured to determine whether or not to retrieve the counter value and whether to retrieve the counter value from an external memory or from a second internal buffer based on the indicator bit values,

wherein the apparatus is further configured to clear said external memory by resetting said indicator bit values from said first internal buffer.

31. The apparatus of claim 30 , wherein the apparatus further comprises the second internal buffer configured to store limited values for each counter,

and wherein the apparatus is further configured to clear said external memory and said second internal buffer by resetting said indicator bit values from said first internal buffer.

32. The apparatus of claim 30 , where in the apparatus further comprises a unidirectional bus for receiving instructions.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2018
From: DDEEG MICROCONSULTING OY
To: ATI TECHNOLOGIES ULC
Reel/Frame 044773/0138 →
CHANGE OF NAME Recorded Nov 18, 2009
From: BITBOYS OY, A FINNISH REGISTERED CO.
To: ATI TECHNOLOGIES (FINLAND) OY
Reel/Frame 023538/0101 →
CHANGE OF NAME Recorded Nov 18, 2009
From: ATI TECHNOLOGIES (FINLAND) OY
To: ADVANCED MICRO DEVICES (FINLAND) OY
Reel/Frame 023538/0112 →
CHANGE OF NAME Recorded Nov 18, 2009
From: ADVANCED MICRO DEVICES (FINLAND) OY
To: DDEEG MICROCONSULTING OY
Reel/Frame 023538/0116 →