Preventing store starvation in a system that supports marked coherence

1. A method for preventing store starvation in a system that supports marked coherence, comprising:

receiving a store instruction to be executed;

determining whether a cache line to which the store is directed is load-marked;

if the cache line is load-marked, delaying the store operation and asserting a store-requested flag in the metadata for the cache line, wherein when the store-requested flag is asserted, no subsequent load-marks can be placed on the cache line; and

completing the store operation when all of the load-marks have been removed from the cache line.

2. The method of claim 1 , wherein asserting the store-requested flag involves first obtaining a writeable copy of the cache line.

3. The method of claim 1 , wherein if a thread is prevented by one or more other threads from completing a store operation after asserting the store-requested flag, the method further comprises using a forward-progress mechanism to allow the thread to proceed with the store operation in a round-robin fashion with the one or more other threads.

4. The method of claim 1 , wherein determining whether the cache line to which the store is directed is load-marked involves receiving a copy of the cache line along with metadata associated with the cache line, wherein the metadata includes prior load-marks and the store-requested flag.

5. The method of claim 4 , wherein determining whether the cache line to which the store is directed is load-marked involves determining whether at least one other thread has placed a load-mark on the cache line, wherein when such a load-mark has been placed on a cache line, the thread attempting to store to the cache line cannot perform any stores.

6. The method of claim 5 , wherein the load-mark is cleared when the at least one other thread that placed the load-mark has completed one or more load operations to the cache line.

7. The method of claim 1 , further comprising clearing the store-requested flag when the store operation has completed.

8. The method of claim 1 , wherein when another thread attempts to load-mark the cache line, the other thread receives a copy of the cache line along with metadata associated with the cache line wherein the metadata includes the store-requested flag.

9. An apparatus that prevents store starvation in a system that supports marked coherence, comprising:

an execution mechanism configured to receive a store instruction to be executed;

a monitoring mechanism coupled to the execution mechanism, wherein the monitoring mechanism is configured to determine whether a cache line to which the store is directed is load-marked;

if the cache line is load-marked, the execution mechanism is configured to delay the store operation and assert a store-requested flag in the metadata for the cache line, wherein when the store-requested flag is asserted, no subsequent load-marks can be placed on the cache line; and

wherein the execution mechanism is configured to complete the store operation when all of the load-marks have been removed from the cache line.

10. The apparatus of claim 9 , wherein the execution mechanism is configured to obtain a writeable copy of the cache line before asserting the store-requested flag.

11. The apparatus of claim 9 , further comprising a forward-progress mechanism coupled to the execution mechanism, wherein if a thread is prevented by one or more other threads from completing a store operation after asserting the store-requested flag, the forward-progress mechanism is configured to allow the thread to proceed with the store operation in a round-robin fashion with the one or more other threads.

12. The apparatus of claim 9 , wherein when determining whether the cache line to which the store is directed is load-marked, the monitoring mechanism is configured to receive a copy of the cache line along with metadata associated with the cache line, wherein the metadata includes prior load-marks and the store-requested flag.

13. The apparatus of claim 12 , wherein when determining whether the cache line to which the store is directed is load-marked, the monitoring mechanism is configured to determine whether at least one other thread has placed a load-mark on the cache line, wherein when such a load-mark has been placed on a cache line, a thread attempting to store to the cache line cannot perform any stores.

14. The apparatus of claim 13 , wherein the execution mechanism is configured to clear a load-mark when the at least one other thread that placed the load-mark has completed one or more load operations to the cache line.

15. The apparatus of claim 9 , wherein the execution mechanism is configured to clear the store-requested flag when the store operation has completed.

16. The apparatus of claim 9 , further comprising a propagating mechanism that propagates a copy of the cache line along with metadata associated with the cache line to threads that attempt to load-mark the cache line, wherein the metadata includes the store-requested flag.

17. A computer system that prevents store starvation in a system that supports marked coherence, comprising:

a processor;

an execution mechanism on the processor, wherein the execution mechanism is configured to receive a store instruction to be executed;

a cache memory coupled to the processor, wherein the cache memory is configured to store data and instructions for the execution mechanism in a number of cache lines;

a monitoring mechanism coupled to the processor and to the cache memory, wherein the monitoring mechanism is configured to determine whether a cache line to which the store is directed is load-marked;

if the cache line is load-marked, the execution mechanism is configured to delay the store operation and assert a store-requested flag in the metadata for the cache line, wherein when the store-requested flag is asserted, no subsequent load-marks can be placed on the cache line; and

wherein the execution mechanism is configured to complete the store operation when all of the load-marks have been removed from the cache line.

18. The computer system of claim 17 , wherein the execution mechanism is configured to obtaining a writeable copy of the cache line before asserting the store-requested flag.

19. The computer system of claim 17 , further comprising a forward-progress mechanism coupled to the execution mechanism, wherein if a thread is prevented by one or more other threads from completing a store operation after asserting the store-requested flag, the forward-progress mechanism is configured to allow the thread to proceed with a store operation in a round-robin fashion with the one or more other threads.

20. The computer system of claim 17 , wherein when determining whether the cache line to which the store is directed is load-marked, the monitoring mechanism is configured to receive a copy of the cache line along with metadata associated with the cache line, wherein the metadata includes prior load-marks and the store-requested flag.

21. The computer system of claim 20 , wherein when determining whether the cache line to which the store is directed is load-marked, the monitoring mechanism is configured to determine whether at least one other thread has placed a load-mark on the cache line, wherein when such a load-mark has been placed on a cache line, a thread attempting to store to the cache line cannot perform any stores.

22. The computer system of claim 21 , wherein the execution mechanism is configured to clear a load-mark when the at least one thread that placed the load-mark has completed one or more load operations to the cache line.

23. The computer system of claim 17 , wherein the execution mechanism is configured to clear the store-requested flag when the store operation has completed.

24. The computer system of claim 17 , further comprising a propagating mechanism that propagates a copy of the cache line along with metadata associated with the cache line to a thread, that attempts load-mark the cache line, wherein the metadata includes the store-requested flag.