IP Library Granted Patent US 8,661,194
Granted Patent B2
US 8,661,194 · App. 11/702,091 · Granted Feb 25, 2014

Cache control method for hybrid HDD, related program, and hybrid disk drive using same

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Quick Facts
Patent No.
US 8,661,194
App. No.
11/702,091
Granted
Feb 25, 2014
Kind
B2
Abstract

A cache control method for a hybrid hard disk drive (HDD) comprising a nonvolatile cache (NVC) and a hard disk. When the hybrid HDD is operating in a non-parallel mode of operation, the control method sequentially searches the NVC and then reads the hard disk for requested data, but when the hybrid HDD is operating in a parallel mode of operation, the control method simultaneously searches the NVC and reads hard disk for the data requested.

Claims (27)

1. A method comprising:

determining whether a hybrid data storage device (HDSD) is in a non-parallel mode of operation or a parallel mode of operation,

when the HDSD is operating in the non-parallel mode of operation, searching a non-volatile cache (NVC) for requested data, retrieving the requested data from a second non-volatile memory when the requested data is not found in the NVC and setting the HDSD to operate in the parallel mode of operation for a next data retrieval request when the requested data has been retrieved from the second non-volatile memory; and

when the HDSD is operating in the parallel mode of operation, simultaneously searching the NVC for the requested data and retrieving the requested data from the second non-volatile memory.

2. The method of claim 1 , wherein upon determining that all of the requested data exists in the NVC during the parallel mode of operation, terminating simultaneous retrieval from the second non-volatile memory.

3. The method of claim 1 , wherein the HDSD further comprises a DRAM cache, and prior to searching the NVC and the second non-volatile memory when the HDSD is operating in the non-parallel mode of operation, searching the DRAM cache for the requested data.

4. The method of claim 1 , wherein the HDSD further comprises a DRAM cache, and prior to searching the NVC and the second non-volatile memory when the HDSD is operating in the parallel mode of operation, searching the DRAM cache for the requested data.

5. The method of claim 1 , wherein when operating in the parallel mode of operation, terminating the parallel mode of operation and implementing the non-parallel mode of operation when power to the HDSD is reset.

6. The method of claim 1 , wherein the determination of whether the HDSD is in the non-parallel mode of operation or the parallel mode of operation is made in relation to a current operating condition of the second non-volatile memory.

7. The method of claim 6 , wherein the current operating condition of the second non-volatile memory is defined in relation to a rotational speed for a spindle motor.

8. A memory device storing instructions, that when executed by a processor cause the processor to perform a method comprising:

determining whether a data storage device having multiple non-volatile storage media (DSD) is operating in a non-parallel mode of operation or a parallel mode of operation,

when the DSD is operating in the non-parallel mode of operation, sequentially searching for requested data in a first non-volatile memory having a non-volatile cache (NVC) and, if the requested data is not found in the NVC then retrieving the requested data from a second non-volatile memory; and

when the DSD is operating in the parallel mode of operation, simultaneously searching the NVC for the requested data and retrieving the requested data from the second non-volatile memory; and

selectively implementing the non-parallel mode of operation and the parallel mode of operation by setting the DSD to operate in the non-parallel mode of operation upon startup of the DSD and setting the DSD to operate in the parallel mode of operation when the requested data has been retrieved from the second non-volatile memory.

9. The memory device of claim 8 , wherein upon determining that all of the requested data exists in the NVC during the parallel mode of operation, terminating simultaneous retrieval from the second non-volatile memory prior to retrieval of all the requested data from the second non-volatile memory.

10. The memory device of claim 8 , wherein the DSD further comprises a DRAM cache, and the method further includes searching the DRAM cache for the requested data prior to searching the NVC or the second non-volatile memory.

11. An apparatus comprising:

a first nonvolatile memory device;

a second nonvolatile memory device;

a controller adapted to selectively implement a non-parallel mode of operation and a parallel mode of operation,

wherein the controller is further adapted to sequentially search the first nonvolatile memory device for data and, if the data is not found in the first nonvolatile memory device then search the second nonvolatile memory device for the data when the apparatus is selected to be operating in the non-parallel mode of operation,

wherein, when the apparatus is operating in the parallel mode of operation, the controller is adapted to simultaneously search the first nonvolatile memory device for the data and search the second nonvolatile memory device for the data; and

implementing the parallel mode of operation by setting the apparatus to operate in the parallel mode of operation when the data has been retrieved from the second non-volatile memory.

12. The apparatus of claim 11 , wherein, when the apparatus is operating in the parallel mode of operation, the controller is further adapted to terminate the search of the second nonvolatile memory device when the apparatus determines that all of the data exists in the first nonvolatile memory device.

13. The apparatus of claim 11 further comprising a DRAM cache, wherein the controller is further adapted to search the DRAM cache prior to searching the first nonvolatile memory device and the second nonvolatile memory device.

14. The apparatus of claim 13 , wherein the controller is further adapted to select the parallel mode of operation after sequentially searching the DRAM cache, the first nonvolatile memory device, and the second nonvolatile memory device when the hybrid HDD is operating in the non-parallel mode of operation and at least a portion of the data is retrieved from the second nonvolatile memory.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE ERRONEOUSLY FILED NO. 7255478 FROM SCHEDULE PREVIOUSLY RECORDED AT REEL: 028153 FRAME: 0689. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 5, 2016
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 040001/0920 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2012
From: SEAGATE TECHNOLOGY INTERNATIONAL
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 029423/0043 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SEAGATE TECHNOLOGY INTERNATIONAL
Reel/Frame 028153/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2007
From: NAM, HYE-JEONG
To: SAMSUNG ELECTRONCIS CO., LTD.
Reel/Frame 018978/0830 →