Switching amplifier system and method
View Patent ↗A switching amplifier system and method is disclosed. In a particular embodiment, a pulse width modulation frame size is determined based on a sample rate of a digital input signal. Data associated with the first digital input signal is modified based on the pulse width modulation frame size. A pulse width modulation signal is generated in response to the modified data.
1. A switching amplifier system, comprising:
a sample rate detection module to detect a sample rate of a digital input signal;
a frame size module to determine a pulse width modulation frame size based on the sample rate of the digital input signal;
an upsampling module to modify data associated with the digital input signal, the upsampling module to produce an upsampled digital input signal;
a noise shaper module to modify the upsampled digital input signal based on the pulse width modulation frame size to produce a noise shaper output signal; and
a pulse width modulation device responsive to the noise shaper output signal.
2. The system of claim 1 , wherein the pulse width modulation device is responsive to a master clock operating at a fixed rate.
3. The system of claim 1 , wherein the digital input signal is a digital audio signal.
4. The system of claim 1 , further comprising a power stage responsive to the pulse width modulation device.
5. The system of claim 4 , wherein the power stage comprises a 3-state switching arrangement and a 3-state switching arrangement control circuit.
6. The system of claim 5 , wherein the 3-state switching arrangement control circuit is an H-Bridge driver.
7. A method for processing a digital signal, the method comprising:
detecting a first sample rate of a first digital input signal;
determining a first pulse width modulation frame size based on the first sample rate;
modifying data associated with the first digital input signal based on the first pulse width modulation frame size; and
generating a first pulse width modulation signal in response to the modified data.
8. The method of claim 7 , further comprising:
detecting a second sample rate of a second digital input signal; and
determining a second pulse width modulation frame size based on the second sample rate.
9. The method of claim 8 , further comprising:
modifying data associated with the second digital input signal based on the second pulse width modulation frame size to produce second modified data; and
generating a second pulse width modulation signal in response to the second modified data.
10. The method of claim 8 , wherein the first sample rate of the first digital input signal is different from the second sample rate of the second digital input signal.
11. The method of claim 7 , further comprising upsampling the first sample rate by an integer multiple of the first sample rate.
12. The method of claim 7 , wherein determining the first pulse width modulation frame size includes performing a calculation with a master clock rate, the first sample rate, and an upsampling ratio.
13. A digital signal processing device for use in connection with a switching amplifier system, the device comprising:
a first summing unit responsive to a digital input signal; and
a multiplier stage responsive to the first summing unit and to a pulse width modulation frame size data, the multiplier stage having an output to provide a noise shaper output signal.
14. The device of claim 13 , wherein the multiplier stage includes a first multiplier unit and a truncation unit.
15. The device of claim 14 , wherein the first multiplier unit is responsive to the first summing unit and the pulse width modulation frame size data.
16. The device of claim 14 , wherein the truncation unit is responsive to the first multiplier unit and the pulse width modulation frame size data.
17. The device of claim 14 , further comprising a feedback stage coupled to the multiplier stage.
18. The device of claim 17 , wherein the feedback stage comprises a second summing unit and a second multiplier unit.
19. The device of claim 18 , wherein the second multiplier unit is responsive to a pulse width modulation frame size reciprocal signal.
20. The device of claim 19 , wherein the feedback stage comprises a low-pass filter that is responsive to the second multiplier unit.
21. The device of claim 18 , wherein the second summing unit is responsive to the first multiplier unit and the noise shaper output signal.
22. A method for processing a digital signal, the method comprising:
performing an addition operation on a digital input signal and a feedback stage signal to produce an addition operation output signal;
performing a multiplication operation on the addition operation output signal and pulse width modulation frame size data to produce a first multiplication operation output signal; and
modifying the first multiplication operation output signal according to the pulse width modulation frame size data to produce a noise shaper output signal.
23. The method of claim 22 , wherein modifying the first multiplication operation output signal comprises performing a truncation operation to reduce the number of bits associated with the first multiplication operation output signal.
24. A method for processing a digital signal, the method comprising:
detecting a sample rate of a digital input signal;
determining a pulse width modulation frame size based on the sample rate; and
generating a pulse width modulation signal based on the pulse width modulation frame size;
wherein generating the pulse width modulation signal comprises performing a compensation operation.
25. The method of claim 24 , wherein the compensation operation comprises re-aligning data associated with a particular frame.
26. The method of claim 24 , wherein the compensation operation is performed periodically.
27. The method of claim 24 , wherein the compensation operation is performed based on the sample rate.
28. The method of claim 24 , wherein the compensation operation is performed based on the pulse width modulation frame size.