Test and debug method and apparatus

1 . A method for performing wireless analyzer spatial position optimization for a network having a particular network topology, comprising the steps of:

recording one or more reference network topology measurements to perform an initial parameter calibration;

estimating a plurality of possible relative positions for the particular network topology;

calculating a link estimator function for each link between a plurality of the possible relative positions; and

calculating recording quality for each received packet at each of the plurality of possible relative positions over each of the links;

whereby a position indicative of an optimal position is determined.

2 . The method of claim 1 , further comprising the steps of:

determining that the particular network topology has changed; and

automatically performing the steps of claim 1 in accordance with the changed network topology.

3 . The method of claim 2 , wherein the network topology changes when a new device is added to the network.

4 . The method of claim 2 , wherein the network topology changes when a device is removed from the network.

5 . The method of claim 2 , wherein the network topology changes when the link estimator function of one of the plurality of positions changes.

6 . The method of claim 1 , wherein the plurality of positions are in a substantially two dimensional plane.

7 . The method of claim 1 , wherein the plurality of positions are in a substantially three dimensional space.

8 . The method of claim 1 , whereby recording quality is optimized at the optimal position.

9 . A method for determining a pattern match between a designated pattern and data in a data sequence of data received in a protocol analyzer, comprising the steps of:

designating a portion of a pattern to be matched as bits that can take on any value;

designating bit values of a portion of the pattern to be matched;

performing a bitwise logical comparison between the pattern to be matched, including the designated bit values and bits that can take on any value, and the data sequence in substantially real time; and

indicating a location in the data stream of any determined matches.

10 . The method of claim 9 , wherein the designated portions of the pattern are constructed into an instruction sequence.

11 . The method of claim 10 , wherein the instruction sequence is implemented in a Field Programmable Gate Array (FPGA).

12 . The method of claim 11 , wherein the instruction sequence comprises the pattern to be matched, including the designated bit values and bits that can take on any value.

13 . The method of claim 12 , wherein a user is notified in substantially real time when a match is determined.

14 . A system for generating traffic for testing a network, comprising:

a traffic generation module for generating traffic to be injected into a network;

wherein one or more parameters of the traffic conforms to a predetermined statistical distribution.

15 . The system of claim 14 , wherein the he number of sent packets over time conforms to the predetermined statistical distribution.

16 . The system of claim 14 , wherein the Payload length of packets sent over time conforms to the predetermined statistical distribution

17 . The system of claim 14 , wherein the time between sent packets conforms to the predetermined statistical distribution.

18 . The system of claim 14 , wherein the predetermined statistical distribution is an exponential distribution used to model uncorrelated packets.

19 . The system of claim 14 , wherein the predetermined statistical distribution is a self-similar distribution used to model correlated packets that are sent in bursts.