IP Library Granted Patent US 7,508,258
Granted Patent B2
US 7,508,258 · App. 11/703,026 · Granted Mar 24, 2009

Amplifier circuit

Assignees: Seiko Instruments Inc.; Gakkouhoujin Chikoujigakuen
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Quick Facts
Patent No.
US 7,508,258
App. No.
11/703,026
Granted
Mar 24, 2009
Kind
B2
Abstract

Provided is a chopper amplifier circuit capable of eliminating an influence of a slew rate of an amplifier and suppressing spike generation to thereby obtain an output signal having little harmonic distortion. The chopper amplifier circuit according to the present invention includes: a first chopper circuit for chopping an input signal by a first pulse and a second pulse shifted from each other in phase by a half cycle, switching a relation of connection between an input terminal pair and an output terminal pair at a timing of the chopping, and outputting the input signal as a modulated signal; an amplifier for amplifying the modulated signal and outputting the modulated signal thus amplified as an amplified signal; a first sample hold circuit for holding the amplified signal at the first pulse and outputting the amplified signal at the second pulse; and a second sample hold circuit for holding the amplified signal at the second pulse and outputting the amplified signal at the first pulse.

Claims (23)

1. A chopper amplifier circuit, comprising:

a chopper circuit for chopping an input signal based on a pulse having a predetermined frequency so as to modulate the input signal;

an amplifier for amplifying the input signal thus modulated;

a first sample hold circuit; and

a second sample hold circuit, wherein:

the chopper amplifier circuit demodulates the modulated signal thus amplified, and outputs the signal thus amplified as an output signal;

the chopper circuit chops the input signal by a first pulse and a second pulse shifted from each other in phase by a half cycle, switches a relation of connection between an input terminal pair and an output terminal pair at a timing of the chopping, and outputs the input signal as a modulated signal;

the amplifier amplifies the modulated signal and outputs the modulated signal thus amplified as an amplified signal;

the first sample hold circuit holds the amplified signal at the first pulse and outputs the amplified signal at the second pulse; and

the second sample hold circuit holds the amplified signal at the second pulse and outputs the amplified signal at the first pulse, and further wherein:

the first sample hold circuit and the second sample hold circuit each include:

a first switch pair into which the amplified signal is inputted;

a hold circuit for holding a voltage level of the amplified signal inputted from the first switch pair; and

a second switch pair for controlling an output of the amplified signal held by the hold circuit, and

one of the first switch pair and the second switch pair is turned off while the other one of the first switch pair and the second switch pair is turned on.

2. A chopper amplifier circuit according to claim 1 , wherein:

the input terminal pair is composed of a first input terminal and a second input terminal;

the output terminal pair is composed of a first output terminal and a second output terminal;

the first input terminal and the first output terminal are connected to each other and the second input terminal and the second output terminal are connected to each other, when the first pulse is inputted; and

the first input terminal and the second output terminal are connected to each other and the second input terminal and the first output terminal are connected to each other, when the second pulse is inputted.

3. A chopper amplifier circuit according to claim 1 , wherein the first sample hold circuit and the second sample hold circuit each hold a voltage level of the amplified signal due to a configuration of a switched capacitor.

4. A chopper amplifier circuit according to claim 1 , wherein:

the first switch pair and the second switch pair, which have output terminals connected to each other, each synthesize the amplified signal outputted from each hold circuit in each of the first sample hold circuit and the second sample hold circuit based on the first pulse and the second pulse, and output the synthesized signal as an output signal.

Assignments (3)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037710/0375 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2007
From: YOSHIZAWA, HIROKAZU; ANZAI, RYOICHI; UCHIDA, TOSHIYUKI; TAKEDA, AKIRA; ARIYAMA, MINORU; IGARASHI, ATSUSHI
To: SEIKO INSTRUMENTS INC.; GAKKOUHOUJIN CHIKOUJIGAKUEN
Reel/Frame 019391/0871 →
Priority Claims (1)
JP 2006-029138 · Feb 7, 2006 · national
Continuity (1)
Related Publication 20070222509A1 · Sep 27, 2007