MOSFET having SOI and method
View Patent ↗Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.
1. A semiconductor device comprising:
an SOI semiconductor substrate including a semiconductor supporting substrate, a buried insulating film formed on the semiconductor supporting substrate, and a silicon active layer formed on the buried insulating film; and
a MOS transistor of a first conductivity disposed on the silicon active layer, the MOS transistor comprising a gate electrode on a gate insulating film; and
an element isolation insulating film surrounding the MOS transistor;
the gate electrode of the MOS transistor comprising a first polysilicon region of a first conductivity disposed above a channel region of the silicon active layer having a constant thickness; and second polysilicon regions of a second conductivity disposed above edge regions of the silicon active layer at which a thickness of the silicon active layer decreases along a width direction of the MOS transistor; and
wherein the element isolation insulating film is disposed between the second polysilicon regions and the edge regions of the silicon active layer.
2. The semiconductor device according to claim 1 , wherein the gate electrode of the MOS transistor has a laminated structure in which a polysilicon layer having a first conductive region and second conductive regions is laminated with a refractory metal silicide layer.
3. The semiconductor device according to claim 1 , wherein the MOS transistor has an impurity diffusion layer of a second conductivity in a source region of a first conductivity.
4. A semiconductor device comprising:
an SOI semiconductor substrate including a semiconductor supporting substrate, a buried insulating film formed on the semiconductor supporting substrate, and a silicon active layer formed on the buried insulating film; and
a first conductivity type MOS transistor which is formed to the silicon active layer and has a gate electrode, wherein
the MOS transistor is surrounded by an element isolation insulating film having a thickness to reach the buried insulating film in a depth direction by a LOCOS process;
the gate electrode of the MOS transistor comprises:
a n-type polysilicon region above a first region of the silicon active layer that comprises a constant thickness; and
first and second p-type polysilicon regions corresponding to LOCOS isolation edges above second regions of the silicon active layer that comprises a thickness that is less that the thickness of the first region of the active silicon layer that is below the n-type polysilicon region; and
the element isolation insulating film is disposed between the first and second p-type polysilicon regions and the second regions of the silicon active layer.
5. The semiconductor device according to claim 4 , wherein the gate electrode of the MOS transistor has a laminated structure in which a polysilicon layer having a first conductive region and a second conductive region is laminated with a refractory metal silicide layer.
6. The semiconductor device according to claim 4 , wherein the MOS transistor comprises a second conductive impurity diffusion layer in a first conductive source region.
7. The semiconductor device according to claim 4 , wherein the element isolation insulating film comprising a gate insulating film between the n-type polysilicon layer and the silicon active region.
8. The semiconductor device according to claim 7 , wherein the gate insulating film comprises a thickness of between approximately 5 nm and approximately 30 nm.
9. The semiconductor device according to claim 1 , wherein the element isolation insulating film comprises a thickness to reach the buried insulating film in a depth direction.
10. The semiconductor device according to claim 1 , wherein the gate insulating film is disposed below the first polysilicon region and above the silicon active layer.