Digital DLL circuit for an interface circuit in a semiconductor memory
A digital DLL circuit includes: a register configured to hold a delay target value; an oscillator; a first counter configured to count an external reference clock or an oscillation output from the oscillator; a second counter configured to count the oscillation output from the oscillator or the external reference clock in every measurement cycle determined by the first counter; and a digitally-controlled variable delay circuit. The DLL circuit further includes a control circuit configured to control the reset and activation of the first counter and the second counter, and control the stop of the first and second counters according to need, based on a count value of the first counter, the control circuit subjecting a count value of the second counter and the delay target value of the register to a digital arithmetic operation, and supplying the variable delay circuit with a result of the arithmetic operation as a delay control value.
1. A digital DLL circuit comprising:
a register configured to hold a delay target value;
an oscillator;
a first counter configured to count an external reference clock or an oscillation output from the oscillator in order to determine a measurement cycle;
a second counter configured to count the oscillation output from the oscillator or the external reference clock in every measurement cycle determined by the first counter;
a digitally-controlled variable delay circuit; and
a control circuit configured to control the reset and activation of the first counter and the second counter, and control the stop of the first and second counters according to need, based on a count value of the first counter, the control circuit subjecting a count value of the second counter and the delay target value of the register to a digital arithmetic operation, and supplying the variable delay circuit with a result of the arithmetic operation as a delay control value.
2. The digital DLL circuit according to claim 1 , wherein
a plurality of the registers that each holds a delay target value is included,
a plurality of the digitally-controlled variable delay circuits are included, and
the control circuit reads out the delay target values of the registers, and the control circuit calculates delay control values that each correspond to a respective one of the delay target values, and supplies the delay control values to the variable delay circuits.
3. The digital DLL circuit according to claim 1 , wherein
the oscillator is a ring oscillator.
4. The digital DLL circuit according to claim 2 , wherein the oscillator is a ring oscillator.