Thin film transistor substrate and method of manufacturing thereof
View Patent ↗A thin film transistor substrate and a method of manufacturing the thin film transistor substrate comprises forming a gate line and a data line intersecting each other with a gate insulating layer interposed and defining a pixel area on the substrate, a thin film transistor electrically connected to the gate line and the data line, and a stepped-structure occurring pattern overlapping at least one of the gate line and the data line; forming a passivation layer having a stepped-structure portion formed by the stepped-structure occurring pattern on the substrate; forming a photoresist pattern having a second stepped-structure portion corresponding to the stepped-structure portion on the passivation layer; patterning the passivation layer using the photoresist pattern as a mask; forming a transparent conductive layer on the substrate; and removing the photoresist pattern where the transparent conductive layer is covered by a stripper penetrating through the stepped-structure portion of the photoresist pattern and forming a pixel electrode connected to the thin film transistor.
1. A thin film transistor substrate comprising:
a gate line formed on a substrate;
a data line intersecting the gate line with a gate insulating layer interposed and defining a sub-pixel area with the gate line;
a thin film transistor comprising a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and a semiconductor pattern forming a channel between the source and drain electrodes and overlapping the data line;
a pixel electrode formed on the substrate of the sub-pixel area and connected to the thin film transistor;
a passivation layer forming the boundary with the pixel electrode and formed in a remaining area except for an area where the pixel electrode is formed; and
a stepped-structure occurring pattern partially overlapping at least one of the gate line and the data line and forming a stepped-structure portion on a surface of the passivation layer.
2. The thin film transistor substrate of claim 1 , wherein the stepped-structure occurring pattern is formed of the same material as the gate line on the substrate so as to partially overlap the data line.
3. The thin film transistor substrate of claim 1 , wherein the stepped-structure occurring pattern is formed of the same material as the data line on the gate insulating layer so as to partially overlap the gate line.
4. The thin film transistor substrate of claim 1 , wherein the stepped-structure occurring pattern includes spaced apart segments.
5. The thin film transistor substrate of claim 4 , further comprising a connecting pattern formed between segments of the stepped-structure occurring patterns so as to connect the stepped-structure occurring patterns to each other.
6. The thin film transistor substrate of claim 5 , wherein the width of the connecting pattern is constant or gradually increases toward the stepped-structure occurring patterns.
7. The thin film transistor substrate of claim 1 , further comprising a gate pad electrically connected to the gate line, wherein the gate pad comprises:
a gate pad lower electrode extended from the gate line; and a gate pad upper electrode formed within a contact hole penetrating the passivation layer and the gate insulating layer and connected to the gate pad lower electrode.
8. The thin film transistor substrate of claim 1 , further comprising a data pad connected to the data line, wherein the data pad comprises:
a data pad lower electrode extended from the data line; and a data pad upper electrode formed within a contact hole penetrating the data pad lower electrode, and the passivation layer and connected to the data pad lower electrode.