Nonvolatile memory cell array architecture for high speed reading
View Patent ↗When different word lines are accessed sequentially, to perform access operations in parallel, a word decoder overlaps a part of activation periods of those word lines. That is, a nonvolatile semiconductor memory is capable of pipeline processing for performing access operations in parallel. All the combinations of bit lines and source lines that are connected to the drains and the sources of nonvolatile memory cells are different from each other. Therefore, even when plural word lines are activated to perform plural read operations in parallel, a memory cell current is allowed to flow only between the drain and the source of a nonvolatile memory cell concerned. As a result, random access in which desired nonvolatile memory cells are accessed sequentially is enabled in a nonvolatile semiconductor memory having a pipeline function for performing plural read operations in parallel.
1. A nonvolatile semiconductor memory comprising:
plural nonvolatile memory cells arranged in matrix form;
plural word lines connected to gates of said nonvolatile memory cells;
plural bit lines connected to drains of said nonvolatile memory cells;
plural source lines connected to sources of said nonvolatile memory cells;
a word decoder which activates a word line according to an address signal, and which, when different word lines are accessed sequentially, overlaps a part of activation periods of said different word lines to perform access operations in parallel;
plural cell groups each of which is a series connection of nonvolatile memory cells and which are arranged in a wiring direction of said plural word lines; and
cell group pairs, each of which is a pair of adjoining cell groups arranged in said wiring direction of said plural word lines, a pair of bit lines of each of the cell group pairs being arranged so as to cross each other in zigzag form, wherein
in each of said cell group pairs, confronting nonvolatile memory cell pairs are connected to different source lines and the sources of said nonvolatile memory cells in each of said cell group pairs are connected to each other, and
all combinations of the bit lines and the source lines connected to the drains and the sources of said nonvolatile memory cells connected to two of said different word lines being optionally selected are different from one another.
2. The nonvolatile semiconductor memory according to claim 1 , wherein:
a source region in which sources are formed and a drain region in which drains are formed are formed alternately between said plural word lines, and
in each of said cell group pairs, a pair of source lines connected to sources of confronting nonvolatile memory cell pairs are formed in the source region and the drain region, respectively.
3. The nonvolatile semiconductor memory according to claim 2 , wherein:
said source line in said drain region has projecting parts which project toward said source region, and
said source line in said drain region is formed by using a wiring layer which is located under a wiring layer of said source line in said source region.
4. The nonvolatile semiconductor memory according to claim 1 , wherein:
in adjoining cell group pairs, the sources of confronting nonvolatile memory cell pairs are formed by common diffusion layers.
5. The nonvolatile semiconductor memory according to claim 4 , further comprising contact parts which are formed between said adjoining cell group pairs and connect, to said diffusion layers, said source lines formed by using a wiring layer, wherein
said source lines are connected to said diffusion layers via said contact parts.
6. The nonvolatile semiconductor memory according to claim 5 , wherein
said contact parts arranged in said wiring direction of said plural word lines are connected to two source lines alternately.
7. The nonvolatile semiconductor memory according to claim 1 , further comprising a source decoder which, in accessing one of the nonvolatile memory cells, sets a voltage of a source line connected to one of the nonvolatile memory cells to be accessed at a ground voltage and sets the other source lines in a floating state.
8. The nonvolatile semiconductor memory according to claim 1 , further comprising a column decoder which, in accessing one of the nonvolatile memory cells, sets a voltage of a bit line connected to one of the nonvolatile memory cells to be accessed at a drain voltage and sets the other bit lines in a floating state.