IP Library Granted Patent US 7,764,938
Granted Patent B2
US 7,764,938 · App. 11/707,865 · Granted Jul 27, 2010

Signaling generation through multiplexing

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Quick Facts
Patent No.
US 7,764,938
App. No.
11/707,865
Granted
Jul 27, 2010
Kind
B2
Abstract

The proposed apparatus and is used for signal generation by multiplexing signals such that there appears no glitches in an output signal. The present apparatus utilizes the knowledge of phase difference between input oscillator signals being multiplexed in order to provide a glitchless output signal. The apparatus comprises a first selection circuit configured to synchronize its response to a first control signal to a next determined event of one of input oscillator signals and convey an input oscillator signal to its output in response to the first control signal. The apparatus comprises a similar selection circuit for each input oscillator signal being multiplexed. Outputs of the selection circuits may be connected to a combining circuit which combines the outputs, thus providing the glitchless output signal.

Claims (66)

1. An apparatus, comprising:

an input interface configured to receive at least a first and a second input oscillator signal having the same frequency but different phases and a first and a second control signal;

a first selection circuit configured to provide a response to a change in the first control signal based on synchronization of the first selection circuit to a next determined event of one of the first and second input oscillator signals and convey the first input oscillator signal to an output of the first selection circuit in response to the first control signal; and

a second selection circuit configured to provide a response to a change in the second control signal based on synchronization of the second selection circuit to a next determined event of one of the first and second input oscillator signals and convey the second input oscillator signal to an output of the second selection circuit in response to the second control signal.

2. The apparatus of claim 1 , further comprising:

a combining circuit operationally coupled to the outputs of the first and the second selection circuit and configured to combine the outputs of the first and the second selection circuit to provide an output signal.

3. The apparatus of claim 2 , further comprising:

a frequency division circuit operationally coupled to an output of the combining circuit and configured to divide a frequency of the output signal of the combining circuit by a determined division factor, wherein an operation of the first and the second selection circuit controls an overall frequency division factor of the apparatus.

4. The apparatus of claim 1 , wherein an operation of the second selection circuit is independent from an operation of the first selection circuit.

5. The apparatus of claim 1 , wherein the first selection circuit comprises:

a synchronization circuit configured to synchronize its response to a change in the first control signal to the event of the first input oscillator signal and output a signal corresponding to the change in the first control signal upon detection of a next input oscillator signal event following the change in the first control signal, and

a logical AND gate having its input ports connected to an output of the synchronization circuit and the input of the first selection circuit.

6. The apparatus of claim 5 , wherein the second selection circuit comprises:

a synchronization circuit configured to synchronize its response to a change in the second control signal to the event of the second input oscillator signal and output a signal corresponding to the change in the second control signal upon detection of a next input oscillator signal event following the change in the second control signal, and

a logical AND gate having its input ports connected to an output of the synchronization circuit and the input of the second selection circuit.

7. The apparatus of claim 6 , wherein the apparatus further comprises a logical OR-gate operationally coupled to outputs of the AND gates of the first and the second selection circuit and configured to combine the outputs of the AND gates to provide an output signal.

8. The apparatus of claim 1 , wherein the determined events of the input oscillator signals of the first and the second selection circuits are synchronized to the same events of the input oscillator signals.

9. The apparatus of claim 8 , wherein the determined events of the input oscillator signals are the rising or falling edges of square wave input oscillator signals.

10. The apparatus of claim 1 , further comprising:

a selection circuit for each one or more additional input oscillator signals, wherein an output of each selection circuit is connected to the combining circuit, and the input interface is configured to receive one or more additional input oscillator signals.

11. The apparatus of claim 10 , wherein each selection circuit is configured to receive two input oscillator signals and a control signal, synchronize to the next determined event of one of the received input oscillator signals and convey the other input oscillator signal to the output of the selection circuit in response to the control signal.

12. The apparatus of claim 1 , wherein the first selection circuit is configured to synchronize its response to the first control signal to the next determined event of the first input oscillator signal and the second selection circuit is configured to synchronize its response to the second control signal to the next determined event of the second input oscillator signal.

13. The apparatus of claim 1 , wherein the apparatus is a phase locked loop.

14. The apparatus of claim 1 , wherein the first and the second input oscillator signals are radio frequency signals.

15. A method, comprising:

receiving at least a first and a second input oscillator signal having different phases and at least a first and a second control signal;

providing a response to a change in the first control signal based on synchronization to a next determined event of one of the first and second input oscillator signals and selecting the first input oscillator signal as a first output signal in response to the first control signal; and

providing a response to a change in the second control signal based on synchronization to a next determined event of one of the first and second input oscillator signals and selecting the second input oscillator signal as a second output signal in response to the second control signal.

16. The method of claim 15 , further comprising:

combining the first and the second output signals to provide a combined output signal.

17. The method of claim 16 , further comprising:

dividing a frequency of the combined output signal; and

controlling a frequency division factor through a selection of the first and the second input oscillator signals.

18. The method of claim 15 , wherein the selection of the first input oscillator signal is independent from the selection of the second input oscillator signal.

19. The method of claim 15 , wherein the response to the first control signal is synchronized to the next determined event of the first input oscillator signal and the response to the second control signal is synchronized to the next determined event of the second input oscillator signal.

20. The method of claim 15 , wherein the determined synchronization events of the input oscillator signals are the same events of the signals.

21. The method of claim 20 , wherein the determined events of the input oscillator signals are the rising or falling edges of square wave input oscillator signals.

22. The method of claim 15 , wherein the first and the second input oscillator signals are radio frequency signals having the same frequency.

23. The method of claim 15 , further comprising:

receiving at least a third input oscillator signal having a phase different from those of the first and the second input oscillator signals; and

synchronizing the response to the first control signal to a determined event of the third input oscillator signal and selecting the first input oscillator signal as the first output signal in response to the first control signal upon the next event of the third input oscillator signal which event follows the change in the control signal.

24. The method of claim 15 , wherein the method is carried out in a frequency synthesizer circuit based on a phase locked loop structure.

25. The method of claim 15 , wherein the first and the second input oscillator signals are radio frequency signals.

26. An apparatus, comprising:

means for receiving at least a first and a second input oscillator signal having different phases and at least a first and a second control signal;

means for providing a response to a change in the first control signal based on synchronization to a next determined event of one of the first and second input oscillator signals and selecting the first input oscillator signal as a first output signal in response to the first control signal; and

means for providing a response to a change in the second control signal based on synchronization to a next determined event of one of the first and second input oscillator signals and selecting the second input oscillator signal as a second output signal in response to the second control signal.

27. An apparatus, comprising:

a voltage-controlled oscillator configured to provide at least one oscillator signal;

a multiplexing circuit operationally coupled with the voltage-controlled oscillator and comprising an input interface configured to receive at least a first input oscillator signal and a second input oscillator signal having the same frequency but different phases and a first and a second control signal, a first selection circuit configured to provide a response to a change in the first control signal based on synchronization of the first selection circuit to a next determined event of one of the first and second input oscillator signals and convey the first input oscillator signal to an output of the first selection circuit in response to the first control signal, and a second selection circuit configured to provide a response to a change in the second control signal based on synchronization of the second selection circuit to a next determined event of one of the first and second input oscillator signals and convey the second input oscillator signal to an output of the second selection circuit in response to the second control signal;

a frequency divider operationally coupled with the multiplexing circuit and configured to divide a frequency of an input oscillator signal by a pre-determined division factor and output a signal indicative thereof;

a reference signal generator configured to provide a reference oscillator signal; and

a comparator circuit operationally coupled with the voltage-controlled oscillator, the frequency divider and the reference signal generator, configured to compare the signal received from the frequency divider with the reference oscillator signal received from the reference signal generator and output a control signal to control the voltage-controlled oscillator according to a difference between the signal received from the frequency divider and the reference oscillator signal.

28. A radio device, comprising:

an input interface configured to receive at least a first and a second input oscillator signal having the same frequency but different phases and a first and a second control signal;

a first selection circuit configured to provide a response to a change in the first control signal based on synchronization of the first selection circuit to a next determined event of one of the first and second input oscillator signals and convey the first input oscillator signal to an output of the first selection circuit in response to the first control signal, and

a second selection circuit configured to provide a response to a change in the second control signal based on synchronization of the second selection circuit to a next determined event of one of the first and second input oscillator signals and convey the second input oscillator signal to an output of the second selection circuit in response to the second control signal.

29. An apparatus, comprising:

voltage-controlled oscillator means for providing at least one oscillator signal;

multiplexing means operationally coupled with the voltage-controlled oscillator and comprising

input interface means for receiving at least a first input oscillator signal and a second input oscillator signal having the same frequency but different phases and a first and a second control signal,

first selection means for providing a response to a change in the first control signal based on synchronization of the first selection circuit to a next determined event of one of the first and second input oscillator signals and for conveying the first input oscillator signal to an output of the first selection circuit in response to the first control signal, and

second selection means for providing a response to a change in the second control signal based on synchronization of the second selection circuit to a next determined event of one of the first and second input oscillator signals and for conveying the second input oscillator signal to an output of the second selection circuit in response to the second control signal;

frequency divider means operationally coupled with the multiplexing circuit and for dividing a frequency of an input oscillator signal by a pre-determined division factor and output a signal indicative thereof;

reference signal generator means for providing a reference oscillator signal; and

comparator means operationally coupled with the voltage-controlled oscillator, the frequency divider and the reference signal generator for comparing the signal received from the frequency divider with the reference oscillator signal received from the reference signal generator and for outputting a control signal to control the voltage-controlled oscillator according to a difference between the signal received from the frequency divider and the reference oscillator signal.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Jun 3, 2021
From: TERRIER SSC, LLC
To: WSOU INVESTMENTS, LLC
Reel/Frame 056526/0093 →
SECURITY INTEREST Recorded Jun 1, 2021
From: WSOU INVESTMENTS, LLC
To: OT WSOU TERRIER HOLDINGS, LLC
Reel/Frame 056990/0081 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: OCO OPPORTUNITIES MASTER FUND, L.P. (F/K/A OMEGA CREDIT OPPORTUNITIES MASTER FUND LP
To: WSOU INVESTMENTS, LLC
Reel/Frame 049246/0405 →
SECURITY INTEREST Recorded May 20, 2019
From: WSOU INVESTMENTS, LLC
To: BP FUNDING TRUST, SERIES SPL-VI
Reel/Frame 049235/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2017
From: NOKIA TECHNOLOGIES OY
To: WSOU INVESTMENTS, LLC
Reel/Frame 043953/0822 →
SECURITY INTEREST Recorded Sep 21, 2017
From: WSOU INVESTMENTS, LLC
To: OMEGA CREDIT OPPORTUNITIES MASTER FUND, LP
Reel/Frame 043966/0574 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2015
From: NOKIA CORPORATION
To: NOKIA TECHNOLOGIES OY
Reel/Frame 035603/0543 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2007
From: HELIO, PETRI; VAANANEN, PAAVO; MIKKOLA, NIKO; KINNUNEN, JOUNI
To: NOKIA CORPORATION
Reel/Frame 019395/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2007
From: HELIO, PETRI; VAANANEN, PAAVO; MIKKOLA, NIKO; MIKKOLA, NIKO
To: NOKIA CORPORATION
Reel/Frame 019358/0797 →