Semiconductor device and fabricating method thereof
View Patent ↗A semiconductor device with a low drain current in the off-state of LDD type accommodating high voltages is provided. On the thermal oxide film, a polysilicon film and a CVD oxide film, and a resist pattern are formed, then the CVD oxide film is side-etched for formation of a CVD oxide film which is after the etching one-size smaller than the polysilicon film. Using the resist pattern as a mask, an impurity is implanted at a high concentration for formation of a source/drain region at a high concentration in an area which does not overlap with the polysilicon film. Further, the resist pattern is removed, and using the CVD oxide film as a mask, an impurity is implanted at a low concentration for formation of an LDD region of a low concentration in an area which overlaps with the gate electrode of the polysilicon film.
1. A fabricating method for a semiconductor device comprising:
selectively forming a field oxide film and an insulation film on a circuit forming surface of a semiconductor substrate;
sequentially forming a gate electrode film and then an oxide film on a surface of said field oxide film and the insulation film;
forming a resist pattern having a predetermined geometry on said oxide film by photolithography;
using said resist pattern as a mask, etching said oxide film and said gate electrode film to form a gate electrode;
using said resist pattern as a mask, etching off a wall face of said oxide film by a predetermined dimension;
using said resist pattern as a mask, performing ion implantation into the circuit forming surface of said semiconductor substrate to form a first diffusion layer of a high concentration; and
removing said resist pattern, and using said oxide film as a mask, performing ion implantation into the circuit forming surface of said semiconductor substrate to form a second diffusion layer of a low concentration.
2. The fabricating method for a semiconductor device of claim 1 , wherein, in the process using said resist pattern as a mask to etch said oxide film and said gate electrode film, to form a gate electrode, a side wall of the gate electrode is tapered such that a bottom face of said gate electrode formed is made smaller in area than said resist pattern.
3. A fabricating method for a semiconductor device comprising:
(a) on a circuit forming face of a silicon substrate, forming a field oxide film in an element isolation region;
(b) in an active region of the circuit forming face, forming a thermal oxide film;
(c) generating a polysilicon film over an entire surface of said field oxide film and the thermal oxide film;
(d) depositing a CVD oxide film over the polysilicon film;
(e) forming a resist layer and using photolithography etching technology on the resist layer to form a resist pattern;
(f) by using said resist pattern as a mask, and said thermal oxide film as an etching stopper, dry etching said CVD oxide film and said polysilicon film to form a gate electrode comprising the CVD oxide film and the polysilicon film remaining after the dry etching;
(g) by using said resist pattern as a mask, side etching only said remaining CVD oxide film;
(h) by using said resist pattern as a mask, performing a first ion implantation at a high concentration, to form source/drain regions; and
(i) after removing said resist pattern, by using said CVD oxide film as a mask, performing a second ion implantation at a low concentration to form an LDD region.
4. The fabricating method for a semiconductor device of claim 3 , wherein the side etching in said (g) is performed by a wet etching process which provides a high etching selectivity ratio between oxide and silicon.
5. The fabricating method for a semiconductor device of claim 3 , wherein the side etching in said (g) is performed by a dry etching process which provides a high etching selectivity ratio between oxide and silicon.
6. The fabricating method for a semiconductor device of claim 3 , wherein, in said first ion implantation in said (h), phosphorous is implanted at a high concentration of about 10 15 ions/cm 2 with a low amount of energy of about 30 to 50 keV, and said silicon substrate is p-type.
7. The fabricating method for semiconductor device of claim 3 , wherein, in said second ion implantation in said (i), phosphorous is implanted at a low concentration of about 10 13 ions/cm 2 with a high amount of energy of about 100 keV, and said silicon substrate is p-type.