Charge pump-type booster circuit
Provided is a charge pump circuit whose power efficiency is not reduced even when a threshold voltage of a transistor is increased by a substrate effect with an increase in the number of stages. A depletion transistor is used as an N-channel transistor included in an inverter of a high-voltage clock generating circuit. A P-channel enhancement transistor is used as a charge transfer device.
1. A charge pump circuit, comprising:
charge transfer transistors connected in series between a voltage input terminal and a voltage output terminal;
coupling capacitors each having one terminal connected with a connection point between the adjacent charge transfer transistors;
a clock generating circuit for alternately inputting clocks whose phases are reversed to each other to the other terminals of the coupling capacitors; and
inverters, each of which includes an N-channel depletion transistor and a P-channel enhancement transistor, for controlling gates of the charge transfer transistors based on signals at the one terminals of the coupling capacitors.
2. A charge pump circuit according to claim 1 , wherein each of the charge transfer transistors comprises an N-channel enhancement transistor.
3. A charge pump circuit according to claim 2 , wherein each of charge transfer transistors located at an nth-stage, in which n is an integer equal to or larger than 2, and subsequent stages comprises a P-channel enhancement transistor.
4. A charge pump circuit according to claim 1 , wherein each of inverters located at an mth-stage, in which m is an integer equal to or larger than 2, and stages previous thereto comprises an N-channel enhancement transistor and a P-channel enhancement transistor.
5. A charge pump circuit according to claim 1 , further comprising an input voltage limiting circuit for limiting an input voltage, which is provided on an input side of a charge transfer transistor located at a first stage.