Semiconductor integrated circuit device and power source wiring method therefor

1. A semiconductor integrated circuit device composed of standard cells arranged therein, the semiconductor integrated circuit device comprising:

a first power source strap supplying a first potential;

a second power source strap placed in parallel relation with the first power source strap and supplying a second potential;

a third power source strap placed between the first and second power source straps in parallel relation therewith and supplying a third potential;

a first standard cell placed between the first and third power source straps and driven with the first and third potentials;

a second standard cell placed between the second and third power source straps and driven with the second and third potentials;

a first cell power source line placed between the first and third power source straps in orthogonal relation to the first power source straps and supplying the first potential from the first power source strap to the first standard cell;

a second cell power source line placed between the second and third power source straps in orthogonal relation to the second power source strap and supplying the second potential from the second power source strap to the second standard cell;

a third cell power source line placed between the first and third power source straps in orthogonal relation to the first power source strap and supplying the third potential from the third power source strap to the first standard cell; and

a fourth cell power source line placed between the second and third power source straps in orthogonal relation to the second power source strap and supplying the third potential from the third power source strap to the second standard cell, wherein

the second standard cell has a transistor size larger than that of the first standard cell,

the second cell power source line has a larger width than the first cell power source line,

the fourth cell power source line has a larger width than the third cell power source line,

the first and second cell power source lines are placed on a straight line,

the third and fourth cell power source lines are placed on a straight line, and

a wiring width of the first cell power source line between the first power source strap and the first standard cell, a wiring width of the second cell power source line between the second power source strap and the second standard cell, a wiring width of the third cell power source line between the third power source strap and the first standard cell, and a wiring width of the fourth cell power source line between the third power source strap and the second standard cell are each constant,

wherein the wiring width of the fourth cell power source line is larger than the wiring width of the third cell power source line,

the third and fourth cell power source lines are formed in the same wiring layer,

the third power source strap is formed in a wiring layer different from the wiring layer in which the third cell power source line is formed,

the third power source strap and the fourth cell power source line are connected to each other via contacts the number of which is in accordance with the wiring width of the fourth cell power source line, and

the third cell power source line is connected to the third power source straps by sharing the contacts with the fourth cell power source line.

2. The semiconductor integrated circuit device of claim 1 , wherein the first, second, and third power source straps are constructed to have the same wiring widths and equal wiring pitches.

3. The semiconductor integrated circuit device of claim 1 , wherein the second standard cell consumes higher power than the first standard cell.

4. The semiconductor integrated circuit device of claim 1 , wherein

the second standard cell consumes higher power than the first standard cell and

the only one second standard cell is placed between the second and third power source straps.