IP Library Granted Patent US 7,412,138
Granted Patent B1
US 7,412,138 · App. 11/713,479 · Granted Aug 12, 2008

Optoelectronic alignment structures for the wafer level testing of optical and optoelectronic chips

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Quick Facts
Patent No.
US 7,412,138
App. No.
11/713,479
Granted
Aug 12, 2008
Kind
B1
Abstract

This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of a wafer. A wafer level test system uses optical and electronic probes to search for and align with an optoelectronic alignment structure. The test system uses a located optoelectronic alignment structure as a reference point to locate other devices on the wafer. The system tests the operation of selected devices disposed on the wafer. The optoelectronic alignment loop is also used as an alignment reference of known performance for an adjacent device of unknown performance.

Claims (25)

1. A method of aligning an optical probe with an optoelectronic alignment structure disposed on an wafer, comprising:

selecting an optical probe with a plurality of waveguides,

selecting an electronic probe with a plurality of electrical conductors,

selecting an optoelectronic alignment structure on the wafer,

where the optoelectronic alignment structure comprises a first optical port, an optical detector and a waveguide coupled between the first optical port and the optical detector,

positioning the optical probe above the wafer at a selected height,

positioning the electronic probe with at least one electrical conductor coupled to the output of the optical detector,

coupling a first light beam down from the first waveguide in the optical probe to the first optical port of the optoelectronic alignment structure on the wafer, where the first light beam propagates through the optoelectronic alignment structure to the optical detector,

and

maximizing the transmission of light through the optoelectronic alignment structure, by adjusting the lateral position of the optical probe with respect to the optoelectronic alignment structure on the wafer.

2. The method according to claim 1 , and further comprising aligning the optical probe to a second optical port disposed on the wafer and maintaining alignment of the optical probe with the first optical port, comprising:

selecting a second waveguide of the plurality of waveguides of the optical probe with a selected distance between the first and second waveguides,

selecting a second optical port on the wafer,

where the distance between the first optical port of the optoelectronic alignment structure and the second optical port is substantially equal to the distance between the first and second waveguides of the optical probe,

positioning the optical probe above the wafer at a selected height,

and

coupling a second light beam from the second waveguide in the optical probe to the second optical port on the wafer, by adjusting the lateral position of the optical probe with respect to the wafer.

3. The method according to claim 2 , and further comprising using the second light beam coupled to the second optical port to test an optical component on the wafer, where the optical component is optically coupled to the second optical port.

4. The method according to claim 1 , and further comprising moving and aligning the optical probe to a second optical port disposed on the wafer, comprising:

selecting a second optical port on the wafer,

determining the positional relationship between the first and second optical ports,

positioning the optical probe above the second optical port at a selected height,

and

coupling a light beam from the optical probe to the second optical port on the wafer, by adjusting the lateral position of the optical probe with respect to the wafer.

5. The method according to claim 4 , and further comprising using the light beam coupled to the second optical port to test an optical component on the wafer, where the optical component is optically coupled to the second optical port.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
RELEASE OF SECURITY INTEREST Recorded Dec 24, 2020
From: SILICON VALLEY BANK
To: LUXTERA, LLC
Reel/Frame 054855/0838 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
SECURITY INTEREST Recorded Mar 29, 2017
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 042109/0140 →
SECURITY AGREEMENT Recorded Jun 17, 2009
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 022835/0340 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2007
From: MALENDEVICH, ROMAN; SUSSMAN, MYLES; GUNN III, LAWRENCE C.
To: LUXTERA, INC.
Reel/Frame 019053/0925 →