IP Library Patent Application 11713572
Patent Application
App. No. 11/713,572

Hardware acceleration for large volumes of channels

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Quick Facts
Patent No.
US None
App. No.
11/713,572
Abstract

A method apparatus and system for hardware acceleration for large volumes of channels is described. In an embodiment, the invention is a method. The method includes monitoring an inbound queue for hardware jobs. The method further includes detecting an interrupt from a hardware component. The method also includes transferring a job from the inbound queue to the hardware component. The method may further include transferring a completed job from the hardware component to an outbound queue. The method may also include providing an indication of completion of a job in an outbound queue.

Claims (62)

1 . A method, comprising:

receiving a channel identifier for a communications channel within a network;

checking the entry corresponding to the channel identifier in an array of channel entries, the array of channel entries indexed by channel identifiers of communications channels;

and

operating the channel corresponding to the channel identifier using channel information from the entry corresponding to the channel identifier in the array of channel entries.

2 . The method of claim 1 , further comprising:

finding the channel information of the entry corresponding to the channel identifier in the array of channel entries.

3 . The method of claim 2 , wherein:

each entry of the array of channel entries includes a pointer suitable for identification of a location of a channel information data structure.

4 . The method of claim 2 , wherein:

each entry of the array of channel entries includes a channel information data structure.

5 . The method of claim 2 , further comprising:

maintaining the entries of the array of channel entries.

6 . The method of claim 5 , wherein:

maintaining the entries of the array of channel entries includes checking a timer of each entry having a corresponding channel information data structure.

7 . The method of claim 5 , wherein:

maintaining the entries of the array of channel entries includes:

checking a timer of a corresponding channel information data structure of an entry of the array of channel entries;

cycling to a next entry of the array of channel entries;

and

repeating the checking and the cycling for each entry of the array of channel entries.

8 . The method of claim 2 , wherein:

operating the channel includes operating a cellular channel in a cellular network.

9 . The method of claim 2 , wherein:

operating the channel includes operating a workstation channel in a computer network.

10 . The method of claim 2 , wherein:

operating the channel includes operating a video channel in a network.

11 . The method of claim 2 , wherein:

operating the channel includes operating a networked device channel in a network.

12 . The method of claim 11 , wherein the networked device of the networked device channel is a workstation.

13 . The method of claim 11 , wherein the networked device of the networked device channel is an intelligent device.

14 . The method of claim 1 , wherein:

operating the channel includes receiving a message, determining what cryptographic operation should be performed on the message, performing a cryptographic operation, and passing the message along the channel.

15 . The method of claim 14 , wherein:

the cryptographic operation is performed by a hardware module responsive to the determining.

16 . The method of claim 14 , wherein:

the cryptographic operation is performed by a software module responsive to the determining.

17 . An apparatus, comprising:

a processor;

a memory coupled to the processor;

a network interface coupled to the processor;

and

wherein the processor is to:

receive a channel identifier for a communications channel within a network;

check the entry corresponding to the channel identifier in an array of channel entries, the array of channel entries indexed by channel identifiers of communications channels;

and

operate the channel corresponding to the channel identifier using channel information from the entry corresponding to the channel identifier in the array of channel entries.

18 . The apparatus of claim 17 , wherein:

the processor is further to:

find the channel information of the entry corresponding to the channel identifier in the array of channel entries.

19 . The apparatus of claim 18 , wherein:

the processor is further to maintain the entries of the array of channel entries.

20 . The method of claim 19 , wherein:

for the processor to maintain the entries of the array of channel entries, the processor is to check a timer of each entry having a corresponding channel information data structure.

21 . The apparatus of claim 19 , wherein:

in order to maintain the entries of the array of channel entries, the processor is to:

check a timer of a corresponding channel information data structure of an entry of the array of channel entries;

cycle to a next entry of the array of channel entries;

and

repeat the check and the cycle for each entry of the array of channel entries.

22 . The apparatus of claim 17 , wherein:

each entry of the array of channel entries includes a pointer suitable for identification of a location of a channel information data structure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2022
From: MOCANA CORPORATION
To: DIGICERT, INC.
Reel/Frame 058946/0369 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2007
From: BLAISDELL, JAMES; TURNER, ADRIAN
To: MOCANA CORPORATION
Reel/Frame 019693/0524 →