Semiconductor device fabrication method
View Patent ↗In fabrication of a semiconductor device which is provided with resistances and MOS transistors on the same substrate, conduction failures of contacts and leaching of wiring metal into a silicon substrate is prevented. Firstly, an underlying structure is prepared. Then, a silicon oxide layer is formed on the underlying structure. Then, a silicon nitride layer is formed on the silicon oxide layer. Then, an inter-layer insulation layer is formed on the silicon nitride layer. Then, a contact hole is formed penetrating through a laminate of the silicon oxide layer, the silicon nitride layer and the inter-layer insulation layer. A thickness of the silicon oxide layer is a value in a range from 32 nm to 48 nm.
1. A method for fabricating a semiconductor device, comprising:
preparing an underlying structure;
forming a silicon oxide layer on the underlying structure;
forming a silicon nitride layer on the silicon oxide layer;
forming an inter-layer insulation layer on the silicon nitride layer; and
forming a contact hole that penetrates through a laminate of the silicon oxide layer, the silicon nitride layer and the inter-layer insulation layer,
wherein a thickness of the silicon oxide layer at a region at which the contact hole is formed is a value in a range from 32 nm to 48 nm.
2. A method for fabricating a semiconductor device, comprising:
preparing an underlying structure at a silicon substrate, the underlying structure being provided with an element isolation region and a MOS transistor formation region which is defined by the element isolation region, and a gate oxide film and a gate electrode being formed at the MOS transistor formation region;
forming a mask oxide layer on the underlying structure;
performing ion-implantation for forming a diffusion layer at a region of the silicon substrate that is to function as a source and drain of a MOS transistor;
forming a resistance isolation oxide layer on the mask oxide layer;
forming a resistance material layer on the resistance isolation oxide layer, the resistance material layer including a predetermined resistance value;
working the resistance material layer for forming a resistance on the resistance isolation oxide layer within a region corresponding to the element isolation region;
forming a silicon nitride layer on the resistance isolation oxide layer and the resistance;
forming an inter-layer insulation layer on the silicon nitride layer; and
forming a contact hole that penetrates through a laminate of the mask oxide layer, the resistance isolation oxide layer, the silicon nitride layer and the inter-layer insulation layer,
wherein a thickness of a silicon oxide layer that is structured by the mask oxide layer and the resistance isolation oxide layer being laminated is a value in a range from 32 nm to 48 nm.
3. The semiconductor device fabrication method of claim 1 , wherein the thickness of the silicon oxide layer is a value in a range from 2.8% to 5.1% of a thickness of the laminate.
4. The semiconductor device fabrication method of claim 2 , wherein the thickness of the silicon oxide layer is a value in a range from 2.8% to 5.1% of a thickness of the laminate.
5. A method for fabricating a semiconductor device, comprising:
preparing an underlying structure;
forming a silicon oxide layer on the underlying structure;
forming a silicon nitride layer on the silicon oxide layer;
forming an aperture portion in the silicon nitride layer, the aperture portion exposing the silicon oxide layer;
forming an inter-layer insulation layer on the silicon nitride layer and the silicon oxide layer that is exposed in the aperture portion; and
forming a contact hole that penetrates through a laminate of the silicon oxide layer, the silicon nitride layer and the inter-layer insulation layer at a region inside the aperture portion,
wherein a diameter of the aperture portion is a value in a range from 1.05 times to 1.3 times a diameter of the contact hole.
6. A method for fabricating a semiconductor device, comprising:
preparing an underlying structure at a silicon substrate, the underlying structure being provided with an element isolation region and a MOS transistor formation region which is defined by the element isolation region, and a gate oxide film and a gate electrode being formed at the MOS transistor formation region;
forming a mask oxide layer on the underlying structure;
performing ion-implantation for forming a diffusion layer at a region of the silicon substrate that is to function as a source and drain of a MOS transistor;
forming a resistance isolation oxide layer on the mask oxide layer;
forming a resistance material layer on the resistance isolation oxide layer, the resistance material layer including a predetermined resistance value;
working the resistance material layer for forming a resistance on the resistance isolation oxide layer within a region corresponding to the element isolation region;
forming a silicon nitride layer on the resistance isolation oxide layer and the resistance;
forming an aperture portion in the silicon nitride layer, the aperture portion exposing the resistance isolation oxide layer;
forming an inter-layer insulation layer on the silicon nitride layer and the resistance isolation oxide layer that is exposed in the aperture portion; and
forming a contact hole that penetrates through a laminate of the mask oxide layer, the resistance isolation oxide layer, the silicon nitride layer and the inter-layer insulation layer at a region inside the aperture portion,
wherein a diameter of the aperture portion is a value in a range from 1.05 times to 1.3 times a diameter of the contact hole.