Semiconductor memory device, refresh control method thereof, and test method thereof
View Patent ↗The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.
1. A semiconductor memory device for sequentially selecting target word lines according to refreshing request signals to thereby perform refresh operations, comprising:
a storage section for storing an address, each address related to each word line which is connected with at least one of memory cells having first data-holding characteristics or second data-holding characteristics; and
a storage switching section for switching the addresses to be stored in the storage section between first addresses related to word lines each of which is connected with the memory cells each having the first data-holding characteristics and second addresses related to word lines each of which is connected with the memory cells each having the second data-holding characteristics, according to a distribution of data-holding characteristics included in memory cells;
wherein a frequency of execution of the refresh operation is judged based on the address to be stored in the storage section by the switching of the storage switching section,
wherein the first address is stored in the storage section when a number of memory cells corresponding to the first address is smaller than a number of the memory cells corresponding to the second address.
2. The semiconductor memory device according to claim 1 , wherein the first data-holding characteristics are data-holding characteristics same as or better than predetermined data-holding characteristics, and the second data-holding characteristics are data-holding characteristics same as or poorer than predetermined data-holding characteristics.
3. The semiconductor memory device according to claim 1 , wherein the second data-holding characteristics are data-holding characteristics same as or better than predetermined data-holding characteristics, and the first data-holding characteristics are data-holding characteristics same as or poorer than predetermined data-holding characteristics.