Method and circuit for line-coupled clock generation
View Patent ↗The invention relates to a method or to a correspondingly equipped circuit for line-coupled generation of a clock (t), wherein the clock (t) is controlled in relation to a synchronization signal (hs) and by means of a closed loop (FLL) with respect to the phase and/or the frequency in relation to the synchronization signal (hs); wherein a plurality (n) of at least two count values (cn, c 0 -c 7 ) is determined, wherein each of the count values (cn, c 0 -c 7 ) is determined with at least one count duration number (z) of consecutive periods of the synchronization signal (hs), and wherein each of the count values (cn, c 0 -c 7 ) is determined offset relative to at least one further count value (cn, c 0 -c 7 ) with a count offset (v) which is different from the count duration number of consecutive periods of the synchronization signal (hs).
1. A method for line-coupled generation of a clock, comprising:
providing the clock in relation to a synchronization signal;
controlling the clock using a closed frequency locked loop with respect to the phase and/or frequency in relation to the synchronization signal;
determining a plurality of count values such that each of the count values is determined for at least one count duration number of consecutive periods of the synchronization signal;
wherein each of the count values is aligned offset relative to at least a further count value by a count offset which is different from the count duration number of consecutive periods of the synchronization signal; and
determining a correction for the clock based on a comparison of the different count values, wherein determining the correction for the clock further comprises determining a clock frequency, and comparing the clock frequency to a predetermined frequency value.
2. The method according to claim 1 , further comprising comparing the values of the different count values in order to determine a phase shifting between the clock and the synchronization signal.
3. The method according to claim 1 , wherein providing the clock in relation to the synchronization signal further comprises generating the clock using an independent clock source and providing the clock such that the clock is synchronized with the synchronization signal.
4. The method according to claim 3 , wherein the synchronization signal comprises a horizontal synchronization signal of a line in a circuit for image processing.
5. The method according to claim 1 , wherein the closed loop is configured to perform frequency measurements.
6. The method according to claim 1 , wherein the count offset corresponds to one period of the clock signal.
7. A method for line-coupled generation of a clock, comprising:
providing the clock in relation to a synchronization signal;
controlling the clock using a closed frequency locked loop with respect to the phase and/or frequency in relation to the synchronization signal;
determining a plurality of count values such that each of the count values is determined for at least one count duration number of consecutive periods of the synchronization signal;
wherein each of the count values is aligned offset relative to at least a further count value by a count offset which is different from the count duration number of consecutive periods of the synchronization signal; and
wherein the plurality of at least two count values comprises a number of count values that is smaller than the total number of the lines of an image signal.
8. The method according to claim 7 , wherein the count duration number of the count values equals the number of count values.
9. The method according to claim 7 , further comprising comparing the values of the different count values in order to determine a phase shifting between the clock and the synchronization signal.
10. The method according to claim 7 , further comprising determining a correction for the clock based on a comparison of the different count values.
11. The method according to claim 10 , wherein determining the correction for the clock further comprises determining a clock frequency, and comparing the clock frequency to a predetermined frequency value.
12. The method according to claim 7 , wherein providing the clock in relation to the synchronization signal further comprises generating the clock using an independent clock source and providing the clock such that the clock is synchronized with the synchronization signal.
13. The method according to claim 12 , wherein the synchronization signal comprises a horizontal synchronization signal of a line in a circuit for image processing.
14. The method according to claim 7 , wherein the closed loop is configured to perform frequency measurements.
15. The method according to claim 7 , wherein the count offset corresponds to one period of the clock signal.
16. A method for line-coupled generation of a clock, comprising:
providing the clock in relation to a synchronization signal;
controlling the clock using a closed frequency locked loop with respect to the phase and/or frequency in relation to the synchronization signal;
determining a plurality of count values such that each of the count values is determined for at least one count duration number of consecutive periods of the synchronization signal;
wherein each of the count values is aligned offset relative to at least a further count value by a count offset which is different from the count duration number of consecutive periods of the synchronization signal; and
wherein the count duration number of the count values is smaller than the number of the image elements in one line of an image signal.
17. The method according to claim 16 , wherein the closed loop is configured to perform frequency measurements.
18. A circuit for line-coupled generation of a clock, comprising:
a clock source configured to provide a clock in relation to a synchronization signal;
a closed frequency locked loop configured to control the clock with respect to the phase and/or frequency in relation to the synchronization signal;
a plurality of counters is provided to determine a corresponding plurality of count values, each count value having at least a count duration number of consecutive periods of the synchronization signal,
wherein the plurality of counters are configured or controlled such that the count value of at least one counter is different relative to the count value of another counter in order to determine a differing count offset of the count duration number of successive periods of the synchronization signal; and
a determination device configured to determine a clock frequency using one or more of the plurality of count values and to compare the clock frequency to a predetermined frequency value.
19. The circuit according to claim 18 , further comprising an image processing circuit configured to provide the clock such that the clock is synchronized with the synchronization signal, the synchronization signal comprising a horizontal synchronization signal of a line.
20. The circuit according to claim 18 , wherein the locked loop (FLL) is configured to carry out frequency measurement and/or frequency control.