Liquid crystal display panel and fabricating method thereof
View Patent ↗A liquid crystal display (LCD) panel is fabricated in a simplified process. The LCD panel includes a thin film transistor (TFT) array substrate with a gate and data lines crossing each other to define a pixel area, a TFT at the crossings of the gate and data lines, a protective film, and a pixel electrode connected to the TFT and formed within a pixel opening that is arranged at the pixel area and formed through the protective film and a gate insulating film. A color filter array substrate is joined to the TFT array substrate. A pattern spacer is between the TFT and color filter array substrate and overlaps at least one of the gate line, the data line, and the thin film transistor. A rib is formed from the same layer as the pattern spacer and overlaps the pixel electrode. Liquid crystal material is provided within the LCD panel.
1. A liquid crystal display panel, comprising:
a thin film transistor array substrate, wherein the thin film transistor array substrate includes:
a gate line on a first substrate;
a data line crossing the gate line and defining a pixel area;
a gate insulating film between the gate and data lines;
a thin film transistor at the crossing of the gate and data lines;
a protective film over the substrate;
a pixel opening defined within the protective film and the gate insulating film, wherein the pixel opening is aligned within the pixel area; and
a pixel electrode within the pixel opening, wherein the pixel electrode is connected to the thin film transistor;
a color filter array substrate joined to the thin film transistor array substrate, wherein the color filter array substrate is spaced apart from the thin film transistor array substrate;
a pattern spacer between the thin film transistor array substrate and the color filter array substrate, wherein the pattern spacer overlaps at least one of the gate line, the data line, and the thin film transistor;
a rib between the thin film transistor array substrate and the color filter array substrate and overlapping the pixel electrode, wherein the pattern spacer and the rib are formed of the same layer; and
liquid crystal material between the thin film transistor array substrate and the color filter array substrate.
2. The liquid crystal display panel as claimed in claim 1 , wherein:
the pattern spacer is on the protective film; and
the rib is on the pixel electrode.
3. The liquid crystal display panel as claimed in claim 2 , wherein:
the pattern spacer contacts the color filter array substrate; and
the rib is spaced apart from the color filter array substrate by a predetermined distance.
4. The liquid crystal display panel as claimed in claim 1 , wherein the pattern spacer and the rib are on the color filter array substrate.
5. The liquid crystal display panel as claimed in claim 4 , wherein:
the pattern spacer contacts the thin film transistor array substrate; and
the rib is spaced apart from the thin film transistor array substrate by a predetermined distance.
6. The liquid crystal display panel as claimed in claim 1 , wherein the thin film transistor array substrate includes a gate pad, wherein the gate pad includes:
a lower gate pad electrode connected to the gate line;
a first contact hole through the protective film and the gate insulating film and exposing the lower gate pad electrode; and
an upper gate pad electrode within the first contact hole and contacting the lower gate pad electrode.
7. The liquid crystal display panel as claimed in claim 1 , wherein the thin film transistor array substrate includes a data pad, wherein the data pad includes:
a lower data pad electrode connected to the data line;
a second contact hole through the protective film and exposing the lower data pad electrode; and
an upper data pad electrode within the second contact hole and contacting the lower data pad electrode.
8. The liquid crystal display panel as claimed in claim 1 , further comprising a storage capacitor including:
the gate line; and
an upper storage electrode overlapping the gate line, wherein the gate insulating film is between the gate line and the upper storage electrode, and wherein the upper storage electrode is connected to the pixel electrode.