Deep STI trench and SOI undercut enabling STI oxide stressor
View Patent ↗A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer ( 307 ) is provided which has a dielectric layer ( 305 ) disposed beneath it. A trench ( 319 ) is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material ( 320 ), thereby forming a trench isolation structure. A channel region ( 326 ) is defined in the semiconductor layer adjacent to the trench isolation structure.
1. A method for imparting stress to the channel region of a semiconductor device, comprising:
providing a semiconductor layer disposed on an insulating layer;
creating a trench which extends through the semiconductor layer and into the insulating layer;
backfilling the trench with a stressor material; and
creating a channel region adjacent to the backfilled trench;
wherein the step of backfilling the trench results in the formation of a trench isolation structure.
2. The method of claim 1 , wherein the stressor material is a tensile stressor.
3. The method of claim 1 , wherein the insulating layer comprises an oxide.
4. The method of claim 1 , wherein the semiconductor device is an NMOS transistor.
5. The method of claim 1 , further comprising:
subjecting the stressor material to densification.
6. The method of claim 5 , wherein the stressor material imparts tensile stress by undergoing shrinkage during densification.
7. The method of claim 1 , wherein the semiconductor layer has a hard mask disposed thereon, and wherein the trench extends through the hard mask.
8. The method of claim 7 , wherein the hard mask comprises a layer of pad oxide having a layer of silicon nitride disposed thereon.
9. The method of claim 1 , wherein creating the trench removes a portion of the insulating layer which extends underneath the semiconductor layer.
10. The method of claim 9 , wherein backfilling the trench causes the stressor material to extend underneath the semiconductor layer.
11. A method for imparting stress to the channel region of an SOI transistor, comprising:
providing a semiconductor stack containing a buried oxide layer, an SOI layer, and a hard mask;
creating a first trench which extends through the hard mask and the SOI layer and which exposes a portion of the oxide layer;
removing a portion of the oxide layer with an etch that undercuts the SOI layer, thereby forming a second trench; and
backfilling the second trench with a stressor material, thereby forming a trench isolation structure.
12. The method of claim 11 wherein, after the trench isolation structure is formed, the stressor material is subjected to densification.
13. The method of claim 11 , wherein the second trench is backfilled such that the stressor material extends underneath the SOI layer.
14. The method of claim 11 , wherein the transistor has a channel region, and wherein the channel region is formed in the SOI layer adjacent to the trench isolation structure.
15. The method of claim 14 , wherein the stressor material imparts tensile stress to the channel region of the transistor.
16. A semiconductor device, comprising:
a semiconductor layer having an insulating layer disposed underneath it;
a channel region defined in said semiconductor layer; and
a trench isolation structure which is adjacent to said channel region and which extends through said first semiconductor layer and into said insulating layer;
wherein said trench isolation structure imparts stress to said channel region wherein said trench isolation structure undercuts the semiconductor layer.
17. The semiconductor device of claim 16 , wherein said semiconductor device is an NMOS transistor, and wherein said trench isolation structure imparts tensile stress to said channel region.
18. A method for imparting stress to the channel region of a semiconductor device, comprising:
providing a semiconductor layer disposed on an insulating layer;
creating a trench which extends through the semiconductor layer and into the insulating layer, wherein the trench is formed by (a) using a first etch to create an opening which extends through the semiconductor layer and which exposes a portion of the insulating layer, and (b) using a second etch to remove a portion of the insulating layer;
backfilling the trench with a stressor material; and
creating a channel region adjacent to the backfilled trench.
19. The method of claim 18 , wherein the second etch undercuts the semiconductor layer.
20. The method of claim 19 , wherein the semiconductor layer has a hard mask disposed thereon, wherein the hard mask comprises a layer of pad oxide having a layer of silicon nitride disposed thereon, wherein the trench extends through the hard mask, and wherein the second etch removes a portion of the pad oxide.
21. The method of claim 19 , wherein the second etch is an essentially isotropic etch.
22. The method of claim 21 , wherein the first etch is a dry etch, and wherein the second etch is a wet etch utilizing aqueous HF.
23. A method for imparting stress to the channel region of a semiconductor device, comprising:
providing a semiconductor layer disposed on an insulating layer;
creating a trench which extends through the semiconductor layer and into the insulating layer;
backfilling the trench with a tensile stressor material; and
creating a channel region adjacent to the backfilled trench.
24. The method of claim 23 , wherein the semiconductor device is an NMOS transistor.
25. The method of claim 23 , further comprising:
subjecting the stressor material to densification.
26. The method of claim 25 , wherein the stressor material imparts tensile stress by undergoing shrinkage during densification.
27. The method of claim 23 , wherein the semiconductor layer has a hard mask disposed thereon, and wherein the trench extends through the hard mask.
28. The method of claim 27 , wherein the hard mask comprises a layer of pad oxide having a layer of silicon nitride disposed thereon.
29. A method for imparting stress to the channel region of a semiconductor device, comprising:
providing a semiconductor layer disposed on an insulating layer;
creating a trench which extends through the semiconductor layer and into the insulating layer;
backfilling the trench with a stressor material; and
creating a channel region adjacent to the backfilled trench;
wherein the semiconductor layer has a hard mask disposed thereon, wherein the trench extends through the hard mask, and wherein the hard mask comprises a layer of pad oxide having a layer of silicon nitride disposed thereon.
30. The method of claim 29 , wherein the stressor material is a tensile stressor.
31. The method of claim 29 , wherein the step of backfilling the trench results in the formation of a trench isolation structure.