Master-slave flip-flop and clocking scheme
View Patent ↗A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CK in and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (t pd ) between the toggling of CK in and a resulting change at the slave latch's output less than it would otherwise be.
1. A master-slave flip-flop, comprising:
a master latch and a slave latch having
respective data inputs, data outputs, and clock inputs, the data output of said master latch connected to the data input of said slave latch, the data input of said master latch being said flip-flop's data input and the data output of said slave latch being said flip-flop's data output,
said master and slave latches receiving clock signals (CKM) and (CKS) at their respective clock inputs,
each latch arranged to be transparent such that it transfers a logic signal applied to its data input to its data output when its clock signal is in a first state, and to latch a logic signal applied to its data input when its clock signal is in a second state; and
a clock buffer arranged to provide clock signals (CKM) and (CKS) such that (CKM) and (CKS) are nominally complementary, said buffer further arranged to skew (CKS) with respect to (CKM) such that said slave latch is made transparent earlier than it would without said skew.
2. The flip-flop of claim 1 , wherein said clock buffer is arranged such that (CKM) and (CKS) toggle in response to the toggling of an input clock CK in from which (CKM) and (CKS) are derived, said buffer arranged to skew (CKS) with respect to (CKM) such that the minimum delay (t pd ) between the toggling of CK in and a resulting change at said slave latch's output is less than it would be without said skew.
3. The flip-flop of claim 2 , wherein said buffer comprises a plurality of series-connected inverters, the input of the first inverter coupled to CK in , said clock signals (CKS) and (CKM) provided by the outputs of respective ones of said inverters.
4. The flip-flop of claim 1 , wherein said clock buffer is further arranged to generate (CKM) with respect to (CKS) such that said master latch is latched after said slave latch is made transparent, such that both latches are temporarily transparent.
5. The flip-flop of claim 1 , wherein each of said latches is transparent when its clock signal is at a logic “high” and is latched when its clock signal is at a logic “low”, such that each latch transitions from latched to transparent on the rising edge of its clock signal and transitions from transparent to latched on the falling edge of its clock signal, said clock buffer thereby arranged such that the rising edge of (CKS) occurs earlier than it would without said skew.
6. The flip-flop of claim 5 , wherein said clock buffer is arranged such that the slew rate of the rising edge of (CKS) is faster than the slew rate of the falling edge of (CKS).
7. The flip-flop of claim 1 , wherein each of said latches is transparent when its clock signal is at a logic “low” and is latched when its clock signal is at a logic “high”, such that each latch transitions from latched to transparent on the falling edge of its clock signal and transitions from transparent to latched on the rising edge of its clock signal, said clock buffer thereby arranged such that the falling edge of (CKS) occurs earlier than it would without said skew.
8. The flip-flop of claim 1 , wherein said flip-flop is part of a memory register which complies with the DDR2 or DDR3 specifications promulgated by JEDEC.
9. A master-slave flip-flop, comprising:
a master latch and a slave latch having respective data inputs, data outputs, and clock inputs, the data output of said master latch connected to the data input of said slave latch, the data input of said master latch being said flip-flop's data input and the data output of said slave latch being said flip-flop's data output,
said master and slave latches receiving clock signals (CKM) and (CKS) at their respective clock inputs,
each latch arranged to be transparent such that it transfers a logic signal applied to its data input to its data output when its clock signal is in a logic “high” state and to latch a logic signal applied to its data input when its clock signal is in a logic “low” state such that each latch transitions from latched to transparent on the rising edge of its clock signal and transitions from transparent to latched on the falling edge of its clock signal;
a clock buffer arranged to receive an input clock CK in and to generate clock signals (CKM) and (CKS) such that (CKM) and (CKS) are derived from and toggle in response to the toggling of CK in and such that (CKM) and (CKS) are nominally complementary, said buffer arranged to skew (CKS) with respect to (CKM) the rising edge of (CKS) occurs earlier than it would without said skew, such that the minimum delay (t pd ) between the toggling of CK in and a resulting change at said slave latch's output is less than it would be without said skew.
10. The flip-flop of claim 9 , wherein said clock buffer is further arranged to generate (CKM) with respect to (CKS) such that said master latch is latched after said slave latch is made transparent, such that both latches are temporarily transparent.
11. The flip-flop of claim 9 , wherein said clock buffer is arranged such that the slew rate of the rising edge of (CKS) is faster than the slew rate of the falling edge of (CKS).