IP Library Granted Patent US 8,051,412
Granted Patent B2
US 8,051,412 · App. 11/716,563 · Granted Nov 1, 2011

Global compiler for controlling heterogeneous multiprocessor

Assignee: Waseda University
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Quick Facts
Patent No.
US 8,051,412
App. No.
11/716,563
Granted
Nov 1, 2011
Kind
B2
Abstract

Performance of a heterogeneous multiprocessor is reduced as much as possible within a short time without any awareness of parallelization matched with a configuration of the heterogeneous multiprocessor. In a heterogeneous multiprocessor system, tasks having parallelism are automatically extracted by a compiler, a portion to be efficiently processed by a dedicated processor is extracted from an input program being a processing target, and processing time is estimated. Thus, by arranging the tasks according to PU characteristics, scheduling for efficiently operating a plurality of PU's in parallel is carried out.

Claims (14)

1. A global compiler for a heterogeneous multiprocessor, for causing a computer to execute the following processings to extract parallelism from an input program and generating an object program corresponding to a plurality of processor units in a system which includes a single or a plurality of types of processor units, the global compiler comprising the processings of:

analyzing the input program by executing, on the computer, a respective code generation compiler prepared beforehand for each type of processor unit included only within the plurality of processor units to extract program portions to be executed for each processor unit, and generating processing allocated processor information for designating the program portion;

generating execution time information estimating execution time of the extracted program portions at the plurality of processor units when an executable portion is extracted from the input program for each dedicated processor unit;

analyzing the input program to extract parallelism of the input program, and allocating the program portions to the plurality of processor units based on the processing allocated processor information and the execution time information;

outputting the allocated program portions as an output code of each processor unit; and

calculating data transfer time between a shared memory of data necessary for each processor unit and a local memory of the processor unit in addition to the estimated execution time obtained by generating the execution time information to generate data transfer time information.

2. The global compiler for a heterogeneous multiprocessor according to claim 1 , further comprising the processing of generating an intermediate program having the data transfer time information inserted as a directive indicating data transfer into the input program corresponding to the data transfer time information.

3. A global compiler for a heterogeneous multiprocessor, for causing a computer to execute the following processings to extract parallelism from an input program and generating an object program corresponding to a plurality of processor units in a system which includes a single or a plurality of types of processor units, the global compiler comprising the processings of:

analyzing the input program by executing, on the computer, a respective code generation compiler prepared beforehand for each type of processor unit included only within the plurality of processor units, to extract program portions to be executed for each processor unit, and generating processing allocated processor information for designating the program portion;

generating execution time information estimating execution time of the extracted program portions at the plurality of processor units when an executable portion is extracted from the input program for each dedicated processor unit;

analyzing the input program to extract parallelism of the input program, and allocating the program portions to the plurality of processor units based on the processing allocated processor information and the execution time information; and

outputting the allocated program portions as an output code of each processor unit;

wherein the processing of generating the execution time information includes processing of calculating program load time and calculating calculator control time of each processor unit based on a hardware architecture of the processor unit to generate program load time information and calculator control time information.

4. The global compiler for a heterogeneous multiprocessor according to claim 3 , wherein the global compiler generates an intermediate program having the program load time information and the calculator control time information inserted as directives indicating the program load time and the calculator control time into the input program corresponding to the program load time information and the calculator control time information.

Assignments (3)
LICENSE Recorded Jun 2, 2021
From: WASEDA UNIVERSITY
To: OSCAR TECHNOLOGY CORPORATION
Reel/Frame 056416/0234 →
LICENSE Recorded Jan 11, 2016
From: WASEDA UNIVERSITY
To: OSCAR TECHNOLOGY CORPORATION
Reel/Frame 037473/0506 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2007
From: KASAHARA, HIRONORI; KIMURA, KEIJI; SHIKANO, HIROAKI
To: WASEDA UNIVERSITY
Reel/Frame 019085/0102 →
Priority Claims (1)
JP 2006-157308 · Jun 6, 2006 · national
Continuity (1)
Related Publication 20070283337A1 · Dec 6, 2007