IP Library Granted Patent US 7,400,045
Granted Patent B2
US 7,400,045 · App. 11/716,704 · Granted Jul 15, 2008

Semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 7,400,045
App. No.
11/716,704
Granted
Jul 15, 2008
Kind
B2
Abstract

In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.

Claims (55)

1. A semiconductor device comprising:

a semiconductor substrate;

a first insulating film provided over the semiconductor substrate;

a first interconnect layer provided in at least an upper portion of the first insulating film;

a second interconnect layer provided in at least an upper portion of the first insulating film;

a first oxidation-resistant conductor film covering the top of the first interconnect layer;

a second oxidation-resistant conductor film covering the top of the second interconnect layer;

a second insulating film provided on the first insulating film, the first oxidation-resistant conductor film, and the second oxidation-resistant conductor film;

a third insulating film provided on the second insulating film; and

a first conductor contact portion passing through the third insulating film and the second insulating film to reach the oxidation-resistant conductor film; and

a second conductor contact portion passing through the third insulating film and the second insulating film to reach the second oxidation-resistant conductor film,

wherein the first conductor contact portion has a greater upper surface area than the second conductor contact portion.

2. The device of claim 1 ,

wherein the oxidation-resistant conductor film is a nitrogen introduced layer produced by introducing nitrogen into an upper region of the interconnect layer.

3. The device of claim 1 ,

wherein the first conductor contact portion is of a rectangular plane.

4. The device of claim 1 ,

wherein the first interconnect layer and the first conductor contact portion constitute a seal ring provided in ring shape.

5. The device of claim 1 ,

wherein an element is provided in the semiconductor substrate, and

the second interconnect layer is electrically connected to the element.

6. The device of claim 1 ,

wherein the second insulating film is an insulating film of silicon compound containing carbon.

7. The device of claim 1 ,

wherein the first conductor contact portion is of a strip-like plane.

8. The device of claim 1 ,

wherein the second conductor contact portion is of a circular plane.

9. The device of claim 1 ,

wherein the second conductor contact portion is of a square plane.

10. The device of claim 1 ,

wherein the second insulating film includes a silicon carbon nitride.

11. The device of claim 1 ,

wherein the second insulating film includes a silicon nitride.

12. The device of claim 1 ,

wherein the second insulating film includes a silicon carbide.

13. The device of claim 1 ,

wherein the second insulating film includes a silicon oxycarbide.

14. The device of claim 1 ,

wherein the first insulating film includes a silicon oxide.

15. The device of claim 1 ,

wherein the substrate is a silicon substrate.

16. The device of claim 1 ,

wherein the first interconnect includes a tantalum nitride.

17. The device of claim 1 ,

wherein the first interconnect includes a tantalum.

18. The device of claim 1 ,

wherein the first interconnect includes a copper.

19. The device of claim 1 ,

wherein the third insulating film includes a carbon-containing silicon oxide.

20. The device of claim 1 ,

wherein the third insulating film includes a FSG.

21. The device of claim 1 ,

wherein the third insulating film includes a BPSG.

22. The device of claim 1 ,

wherein the third insulating film includes a porous film.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2024
From: NUVOTON TECHNOLOGY CORPORATION JAPAN
To: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
Reel/Frame 068118/0314 →
CHANGE OF NAME Recorded Jun 12, 2024
From: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 067711/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →