IP Library Granted Patent US 7,800,191
Granted Patent B2
US 7,800,191 · App. 11/716,743 · Granted Sep 21, 2010

Solid-state imaging device and method for driving the same

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Quick Facts
Patent No.
US 7,800,191
App. No.
11/716,743
Granted
Sep 21, 2010
Kind
B2
Abstract

A pixel array is provided in which cells are arranged in a matrix. Each cell includes a photodiode, an FD, a transfer transistor, a reset transistor, an amplifying transistor having a gate electrode connected to the FD, a drain connected to a power supply line, and a source connected to a vertical signal line, and an FD wire. The FD wire is provided in a first wiring line, and the vertical signal line is provided in a second wiring line positioned over the first wiring layer. Since the potential of the FD wire follows the potential of the vertical signal line, it is possible to suppress a variation in capacitance occurring in the FD when a position of the vertical signal is shifted, depending on a position of the cell.

Claims (40)

1. A solid-state imaging device comprising:

a pixel array including photodiodes for accumulating an amount of electric charges corresponding to the intensity of received light, floating diffusions to which electric charges accumulated by the photodiodes are transferred, transfer transistors for controlling transfer of electric charges from the photodiodes to the floating diffusions, and amplifying transistors having a source from which a signal corresponding to electric charges transferred to the floating diffusion is output, wherein a plurality of cells are provided in the pixel array;

a plurality of power supply lines provided over the pixel array and connected to drains of the amplifying transistors;

a plurality of vertical signal lines provided over the pixel array and connected to sources of the amplifying transistors; and

a plurality of floating diffusion wires provided over the pixel array, connecting gate electrodes of the amplifying transistors and the floating diffusions, wherein

the plurality of power supply lines and the plurality of vertical signal lines extend in a column direction,

first photodiode groups of the photodiodes are between pairs of power supply lines,

second photodiode groups of the photodiodes are between pairs of vertical signal lines,

the pairs of power supply lines and the pairs of vertical signal lines are positioned alternately, and

the plurality of power supply lines and the plurality of vertical signal lines are shifted to the center of the pixel array.

2. The solid-state imaging device of claim 1 , wherein

the plurality of power supply lines, the plurality of floating diffusion wires and the plurality of vertical signal lines are formed in a first wiring layer.

3. The solid-state imaging device of claim 1 , wherein

the pair of power supply lines are connected with each other.

4. The solid-state imaging device of claim 1 , wherein

the plurality of power supply lines is independent individually.

5. The solid-state imaging device of claim 1 , wherein

the plurality of vertical signal lines is independent individually.

6. The solid-state imaging device of claim 1 , wherein

the plurality of power supply lines has branch portions which are located between photodiodes adjacent in vertical direction.

7. The solid-state imaging device of claim 1 , wherein

the plurality of vertical signal lines has branch portions which are located between photodiodes adjacent in vertical direction.

8. The solid-state imaging device of claim 1 , further comprising:

transfer gate electrodes; and

transfer gate electrode wires, wherein

the transfer gate electrode wires extend in horizontal direction.

9. The solid-state imaging device of claim 8 , wherein

the transfer gate electrodes and the transfer gate electrode wires are formed at the same time.

10. The solid-state imaging device of claim 1 , further comprising:

reset gate electrodes; and

reset gate electrode wires, wherein

the reset gate electrode wires extend in horizontal direction.

11. The solid-state imaging device of claim 10 , wherein

the reset gate electrodes and the reset gate electrode wires are formed at the same time.

12. The solid-state imaging device of claim 1 , further comprising:

a substrate contact wire formed in a second wiring layer and between the photodiodes.

13. The solid-state imaging device of claim 12 , wherein

the substrate contact wire is located between the photodiodes in vertical direction.

14. The solid-state imaging device of claim 12 , wherein

the substrate contact wire is located between the photodiodes in horizontal direction.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2007
From: OHTSUKI, HIROHISA; KATSUNO, MOTONARI; MIYAGAWA, RYOHEI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 019853/0764 →