Semiconductor integrated circuit having a BIST circuit
View Patent ↗A semiconductor integrated circuit, includes a first external terminal which inputs a test signal, a second external terminal which external inputs a clock signal, a self-test circuit which conducts a self-test based on the clock signal which is input through the second external terminal, a third external terminal which outputs, to the outside, a test judgment signal which is output from the self-test circuit, an external output control circuit which controls output of the test judgment signal from the third external terminal on the basis of the test signal which is input through the first external terminal and a test completion signal which is output from the self-test circuit, and a clock signal input control circuit which controls input, to the self-test circuit, of the clock signal which is input through the second external terminal, on the basis of the test judgment signal and the test completion signal.
1. A semiconductor integrated circuit, comprising:
a first external terminal which inputs a test signal;
a second external terminal which inputs a clock signal;
a self-test circuit which conducts a self-test based on the clock signal which is input through the second external terminal;
a third external terminal which outputs, to the outside, a test judgment signal which is output from the self-test circuit;
an external output control circuit which controls output of the test judgment signal from the third external terminal on the basis of the test signal which is input through the first external terminal and a test completion signal which is output from the self-test circuit; and
a clock signal input control circuit which controls input, to the self-test circuit, of the clock signal which is input through the second external terminal, on the basis of the test judgment signal and the test completion signal.
2. The semiconductor integrated circuit according to claim 1 , wherein the external output control circuit includes:
an external terminal control circuit which outputs an enable signal in accordance with the test signal and the test completion signal; and
a tri-state buffer which controls output, from the third external terminal, of the test judgment signal in accordance with a state of the enable signal which is output from the external terminal control circuit.
3. The semiconductor integrated circuit according to claim 2 , wherein the tri-state buffer is rendered in a high-impedance state when the enable signal is in an inactive state.
4. The semiconductor integrated circuit according to claim 2 , wherein the tri-state buffer allows the test judgment signal to be output from the third external terminal to the outside when the enable signal is in an active state.
5. The semiconductor integrated circuit according to claim 1 , wherein the clock signal input control circuit inputs the clock signal to the self-test circuit when both of the test judgment signal and the test completion signal are normal.
6. The semiconductor integrated circuit according to claim 1 , wherein the clock signal input control circuit includes:
a control signal output circuit which outputs a control signal in accordance with the test judgment signal and the test completion signal; and
a PLL circuit which outputs a frequency-divided clock signal which is generated by frequency-dividing the clock signal which is input through the second external terminal, when receiving the control signal from the control signal output circuit; and
wherein the frequency-divided clock signal which is output from PLL circuit is input to the self-test circuit.