Data processing apparatus including reconfigurable logic circuit
View Patent ↗There is provided a data processing apparatus ( 1 ) including a logic circuit ( 10 ) that is reconfigurable in each cycle and a library ( 2 ) that stores hardware control information ( 20 ). The hardware control information ( 20 ) includes a plurality of pieces of cycle-based mapping information ( 21 ) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit ( 10 ) and configuration selection information ( 22 ) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus ( 1 ) includes a control unit ( 11 ) that reconfigures at least part of the logic region ( 10 ) using at least one of the plurality of pieces of cycle-based mapping information ( 21 ) according to a request in each cycle based on the configuration selection information ( 22 ).
1. A generation system for generating hardware control information for controlling a reconfigurable logic circuit, the generation system comprising:
a functional unit for generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application; and
a functional unit for generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, wherein the functional unit for generating the hardware control information includes generating a piece of configuration selection information in each cycle and merging the piece of configuration selection information with a piece of cycle-based mapping information.
2. The generation system according to claim 1 , further comprising a functional unit for generating composite cycle-based mapping information by extracting, out of the plurality of pieces of cycle-based mapping information, pieces of cycle-based mapping information that are capable of being merged without obstructing functions in each cycle and merging the pieces of cycle-based mapping information extracted.
3. The generation system according to claim 1 , wherein the functional unit for generating the circuit information includes resolving RTL for executing the application on a cycle basis and generating information of the plurality of cycle-based circuits.
4. A generation system for generating hardware control information for controlling a reconfigurable logic circuit, the generation system comprising:
a functional unit for generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application; and
a functional unit for generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, wherein the functional unit for generating the circuit information includes generating information of the plurality of cycle-based circuits based on a control data flow graph for executing the application.
5. The generation system according to claim 4 , further comprising a functional unit for generating composite cycle-based mapping information by extracting, out of the plurality of pieces of cycle-based mapping information, pieces of cycle-based mapping information that are capable of being merged without obstructing functions in each cycle and merging the pieces of cycle-based mapping information extracted.
6. The generation system according to claim 4 , wherein the functional unit for generating the circuit information includes resolving RTL for executing the application on a cycle basis and generating information of the plurality of cycle-based circuits.
7. A computer implemented method of generating hardware control information for controlling a reconfigurable logic circuit, the method comprising the steps of:
the computer generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application; and
the computer generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, wherein the step of generating the hardware control information includes generating a piece of configuration selection information in each cycle and merging the piece of configuration selection information with a piece of cycle-based mapping information.
8. The method according to claim 7 , further comprising a step of generating composite cycle-based mapping information that includes extracting, out of the plurality of pieces of cycle-based mapping information, pieces of cycle-based mapping information that are capable of being merged without obstructing functions in each cycle and merging the pieces of cycle-based mapping information extracted.
9. The method according to claim 7 , wherein the step of generating the circuit information includes generating information of the plurality of cycle-based circuits based on a control data flow graph for executing the application.
10. The method according to claim 7 , wherein the step of generating the circuit information includes resolving RTL for executing the application on a cycle basis and generating information of the plurality of cycle-based circuits.