IP Library Granted Patent US 8,633,545
Granted Patent B2
US 8,633,545 · App. 11/719,923 · Granted Jan 21, 2014

Saddle type MOS device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,633,545
App. No.
11/719,923
Granted
Jan 21, 2014
Kind
B2
Abstract

The present invention relates to a nano-scale MOS device having a saddle structure. Particularly, the invention relates to a high-density, high-performance MOS device having a novel structure capable of improving the scaling-down characteristic and performance of the MOS device, in which a channel and gate structure is formed in the shape of a saddle. The inventive MOS device is mainly characterized in that a channel region is recessed, a gate insulating film and a gate electrode are formed on the surface and sides of the recessed channel, and the gate electrode is self-aligned with the recessed channel. Namely, in the disclosed MOS device, a portion of the insulating film around the recessed channel is selectively removed to expose the surface and sides of the recessed channel. According to the present invention, the scaling-down characteristic of the device is excellent and current drive capability is greatly increased since a channel through which an electric current can flow is formed on the surface and sides of the recessed channel. Also, the ability of the gate electrode to control the channel is enhanced. Accordingly, the invention can improve device characteristics.

Claims (16)

1. A MOS device comprising:

a silicon substrate;

a wall type silicon body protruding substantially perpendicular to the silicon substrate, the wall type silicon body having a height, a length, a width, a top surface and side surfaces, the wall type silicon body having a source region, a channel region and a drain region of the MOS device;

a first insulating film formed on the top surface and the side surfaces of the wall type silicon body;

a gate electrode formed on the channel region while having the first insulating film between the channel region and the gate electrode,

wherein a top surface of the channel region, along with the first insulating film formed thereon, is depressed toward the silicon substrate to form a recess region to thereby define a recessed channel region near the recess region, and the gate electrode extends into the recess region and further extend, beyond the entire recess region, toward the silicon substrate along side surfaces of the recessed channel region to form side-surface portions of the gate electrode, thereby forming a saddle-like form of gate electrode at the recessed channel region;

a silicon nitride film formed directly on the first insulation film beyond both terminal ends of the side-surface portions of the gate electrode toward the silicon substrate; and

a second insulation film formed on the silicon nitride film.

2. The MOS device of claim 1 , wherein the first insulation film is extended onto the silicon substrate and the silicon nitride film is extended onto the first insulation film formed on the silicon substrate.

3. The MOS device of claim 1 , wherein the gate electrode further extends from the recess region toward the drain and source regions along the side surface of the wall type silicon body.

4. The MOS device of claim 1 , wherein the silicon nitride film and the second insulating film each have a recess corresponding to the recess region, and the gate electrode extends into the recess provided in the silicon nitride film and the second insulating film.

5. The MOS device of claim 1 , wherein bottom corners of the recess region have one selected from the group consisting of an obtuse angle, an acute angle, and a rounded shape.

6. The MOS device of claim 1 , wherein the wall-type silicon body has a cross-section gradually wider toward the silicon substrate from a point beyond the both terminal ends of the side-surface portions of the gate electrode.

7. The MOS device of claim 1 , wherein the gate electrode is formed of at least one selected from the group consisting of polysilicon, amorphous silicon, poly-SiGe, amorphous SiGe, metal, metal alloy, and silicide with metal, or the gate electrode has a stacked formation formed of at least two selected from the group consisting of the polysilicon, the amorphous silicon, the poly-SiGe, the amorphous SiGe, the metal, the metal alloy, and the silicide with metal.

8. The MOS device of claim 1 , wherein a transverse width of the gate electrode above the top surface of the wall-type silicon body is larger than a width of the gate electrode below the top surface of the wall-type silicon body.

9. The MOS device of claim 1 , wherein the gate electrode is self-aligned with the recessed channel region.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CORPORATION
Reel/Frame 054486/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2020
From: RPX CORPORATION
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 051842/0494 →
RELEASE OF LIEN ON PATENTS Recorded Oct 21, 2019
From: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
To: RPX CORPORATION
Reel/Frame 050777/0983 →
SECURITY INTEREST Recorded Jun 29, 2018
From: RPX CORPORATION
To: JEFFERIES FINANCE LLC
Reel/Frame 046486/0433 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2017
From: SNU R&DB FOUNDATION
To: RPX CORPORATION
Reel/Frame 040993/0697 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2010
From: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
To: SNU R&DB FOUNDATION
Reel/Frame 025333/0926 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2007
From: LEE, JONG-HO
To: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
Reel/Frame 019548/0337 →