Granted Patent B2

US 8,018,247 · App. 11/720,129 · Granted Sep 13, 2011

Abstract

Claims (25)

1. A method for reducing power consumption of transistor-based circuit, the method comprises:

receiving a low power mode indication;

determining whether to supply power to at least a portion of the transistor-based circuit based on a reset value of the transistor-based circuit and a state of the transistor-based circuit prior to the receiving of the low power mode indication; and

selectively providing power to at least a portion of the transistor-based circuit based on the determination of whether to supply power to at least a portion of the transistor-based circuit.

2. The method according to claim 1 further comprising configuring the transistor-based circuit reset value such as to reduce power consumption.

3. The method according to claim 1 , wherein determining comprises providing a feedback signal representative of the state of the transistor-based circuit to a power gating circuit.

4. The method according to claim 1 , further comprising providing multiple transistor-based circuits and configuring their reset value such as to reduce power consumption of at a certain amount of transistor-based circuits during a low power state.

5. The method according to claim 4 , wherein the certain amount exceeds a half of the multiple transistor-based circuits.

6. The method according to claim 4 , wherein the certain amount of transistor-based circuits is shut down during the low power mode.

7. The method according to claim 1 wherein the transistor-based circuit is a memory circuit.

8. The method according to claim 7 wherein the portion comprises a register cell.

9. An apparatus for reducing power consumption of a transistor-based circuit, the apparatus being coupled to the transistor-based circuit, and is adapted to receive a low power mode indication, wherein the apparatus comprises:

a determining circuit to determine whether to supply power to at least a portion of the transistor-based circuit based on a state of the transistor-based circuit prior the receiving of the low power mode indication; and

a power gating circuit, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination of whether to supply power.

10. The apparatus according to claim 9 , further comprising a reset circuit to affect the reset state of the transistor-based circuit.

11. The apparatus of claim 10 wherein the reset circuit is responsive to a state of the transistor-based circuit prior the receiving of the low power mode indication.

12. The apparatus according to claim 9 , wherein the transistor-based circuit is a memory circuit.

13. The apparatus according to claim 9 , wherein the portion comprises a register cell.

14. An integrated circuit comprising:

multiple transistor-based circuits, comprising:

multiple apparatuses for reducing power consumption of the multiple transistor-based circuits, wherein each apparatus comprises a determining circuit to determine whether to supply power to at least a portion of the multiple transistor-based circuits based on a state of the multiple transistor-based circuits prior the receiving of the low power mode indication; and

a power gating circuit; and

wherein a reset value of the multiple transistor-based circuits is configured such as to reduce power consumption of at a certain amount of the multiple transistor-based circuits during a low power state.

15. The integrated circuit of claim 14 , wherein the certain amount exceeds a half of the multiple transistor-based circuits.

16. The integrated circuit according to claim 14 , wherein the certain amount of the multiple transistor-based circuits is shut down during the low power mode.

Assignments (29)