Method of forming an interconnect structure on an integrated circuit die
View Patent ↗A method of forming an interconnect structure, comprising forming a first interconnect layer ( 123 ) embedded in a first dielectric layer ( 118 ), forming a dielectric tantalum nitride barrier ( 150 ) by means of atomic layer deposition on the surface of the first interconnect ( 123 ), depositing a second dielectric layer ( 134 ) over the first interconnect ( 123 ) and the barrier ( 150 ) and etching a via ( 154 ) in the dielectric layer ( 134 ) to the barrier ( 150 ). The barrier ( 150 ) is then exposed to a treatment through the via ( 154 ) to change it from the dielectric phase to the conductive phase ( 180 ) and the via ( 154 ) is subsequently filled with conductive material ( 123 ).
1. A method of forming an interconnect structure on an integrated circuit die, the method comprising:
selectively depositing a dielectric barrier on a surface of a first conductive interconnect embedded in a first dielectric layer,
depositing a second dielectric layer over said first dielectric layer and said dielectric barrier,
etching a via in said second dielectric layer to said dielectric barrier,
performing a process to transform material in said dielectric barrier to a conductive material so as to form a conductive connecting portion, and
introducing another conductive material into said via etched in said second dielectric layer to form a second conductive interconnect.
2. A method according to claim 1 , wherein the dielectric barrier is deposited by means of an atomic layer deposition process.
3. A method according to claim 1 , wherein prior to said transformation process, another dielectric barrier is deposited at least on the side walls of the via.
4. A method according to claim 1 , wherein the dielectric barrier is tantalum nitride which is initially deposited on a surface of the conductive interconnect in its non-conductive Ta 3 N 5 phase.
5. A method according to claim 1 , wherein said first and second conductive interconnects are formed of copper.
6. A method according to claim 1 , wherein the first and second dielectric layers comprise a silicon oxide based dielectric.
7. A method according to claim 4 , wherein said Ta 3 N 5 phase of the dielectric barrier is subsequently transformed by a plasma treatment, into the conductive TaN phase.
8. An integrated circuit die including an interconnect structure formed according to the method of claim 1 , wherein the step of etching to said dielectric barrier results in an etched upper surface of the conductive material as transformed.