Cache memory control method and cache memory control device
View Patent ↗An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps 2 - 1 and 2 - 2 ), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step 2 - 6 ). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step 2 - 3 ), or a second hit/miss determination is performed by accessing all the ways (Step 2 - 4 ).
1. A cache memory control method which is intended for a cache memory comprising at least two memory units, and in which allowance/disallowance of a cache refill is set in advance for each memory unit, the memory unit of the cache memory, for which the cache refill is set to be allowed, is selectively accessed to perform a first cache hit/miss determination, and the access to the cache memory is ended at the time of a cache hit,
wherein when the first cache hit/miss determination results in a cache miss, the memory unit of the cache memory, for which the cache refill is disallowed, is selectively accessed to perform a second cache hit/miss determination.
2. A cache memory control method for a cache memory comprising at least two memory units, in which allowance/disallowance of a cache refill is set in advance for each memory unit, the memory unit of the cache memory, for which the cache refill is set to be allowed, is selectively accessed to perform a first cache hit/miss determination, and the access to the cache memory is ended at the time of a cache hit,
wherein when the first cache hit/miss determination results in a cache miss, all the memory units in the cache memory are accessed to perform a second cache hit/miss determination.
3. A cache memory control device, comprising:
a cache memory comprising at least two memory units;
a cache refill allowance/disallowance setting section for setting allowance/disallowance of a cache refill for each memory unit of the cache memory;
a memory unit selecting section for enabling a selective access to the memory unit of the cache memory, for which the cache refill is set to be allowed by the cache refill allowance/disallowance setting section in accordance with a setting state of the cache refill allowance/disallowance setting section; and
a hit/miss control section for performing a first cache memory hit/miss determination on the memory unit for which the cache refill is set to be allowed, and for ending the access to the cache memory at the time of a cache hit,
wherein when a cache miss is determined by the hit/miss control section, the memory unit selecting section enables a selective access to the memory unit of the cache memory, for which the cache refill is disallowed, and the hit/miss control section performs a second cache hit/miss determination on the memory unit for which the cache refill is disallowed.
4. A cache memory control device, comprising:
a cache memory comprising at least two memory units;
a cache refill allowance/disallowance setting section for setting allowance/disallowance of a cache refill for each memory unit of the cache memory;
a memory unit selecting section for enabling a selective access to the memory unit of the cache memory, for which the cache refill is set to be allowed by the cache refill allowance/disallowance setting section in accordance with a setting state of the cache refill allowance/disallowance setting section; and
a hit/miss control section for performing a first cache memory hit/miss determination on the memory unit for which the cache refill is set to be allowed, and for ending the access to the cache memory at the time of a cache hit,
wherein when a cache miss is determined by the hit/miss control section, the memory unit selecting section enables an access to all the memory units in the cache memory, and the hit/miss control section performs a second cache hit/miss determination on all the memory units in the cache memory.