Compiling method, compiling apparatus and computer system for a loop in a program

1. A method for compiling a program including a loop, the loop in the program including K instructions (K≧2) and repeating for M times (M≧2), comprising the steps of:

a) performing resource conflict analysis to the K instructions in the loop;

i) wherein in the case that K is an even number, determining successively and respectively whether functional units for executing an ith instruction (1≦i≦K/2) and those for executing a jth instruction ((K/2+1)≦j≦K), in the K instructions, are in conflict; and

determining successively whether registers for executing the ith instruction (1≦i≦K/2) and registers for executing any one from the jth instruction ((K/2+1)≦j≦K) to the Kth instructions, in the K instructions, are in conflict; and

ii) wherein in the case that K is an odd number, determining successively and respectively whether the functional units for executing the ith instruction (1≦i≦((K+1)/2−1)) and those for executing the jth instruction (((K+1)/2+1)≦j≦K), in the K instructions, are in conflict; and

determining successively whether registers for executing the ith instruction (1≦i≦(K+1)/2−1) and registers for executing any one from the jth instruction (((K+1)/2+1)≦j≦K) to the Kth instruction, in the K instructions, are in conflict;

b) dividing the K instructions in the loop into a first combined instruction section, a connection instruction section and a second combined instruction section, wherein there is no resource conflict between instructions in the first combined instruction section and the instructions in the second combined instruction section respectively; and

c) compiling the program, wherein the instructions in the first combined instruction section in a cycle N (N=2, 3, . . . M) and the instructions in the second combined instruction section in a cycle N−1 are compiled in parallel respectively.

2. The method according to claim 1 , wherein the instructions in the connection instruction section and the instructions in the first or second combined instruction sections have resource conflicts.

3. The method according to claim 2 , wherein the instructions in the connection instruction section is zero.

4. The method according to claim 1 , wherein the instructions in the first combined instruction section and in the second combined instruction section are equal.

5. The method according to claim 1 , wherein instructions in the connection instruction section in respective cycles are compiled sequentially.

6. The method according to claim 1 , wherein the instructions, in the first combined instruction section of a first cycle and in the second combined instruction section of a Mth cycle, are compiled sequentially.

7. A compiling apparatus for compiling a program including a loop, the loop in the program including K instructions (K≧2) and repeating for M times (M≧2), the compiling apparatus comprising:

a resource conflict analysis unit configured for performing resource conflict analysis on the K instructions in the loop by a processor, the resource conflict analysis unit comprises:

a functional unit conflict analysis configured for determining successively and respectively whether functional units for executing an ith instruction determined by (1≦i≦K/2) when K is an even number or by (1≦i≦((K+1)/2−1)) when K is an odd number and functional units for executing a jth instruction determined by ((K/2+1)≦j≦K) when K is an even number or by (((K+1)/2+1)≦j≦K) when K is an odd number, in the K instructions, have conflicts; and

a register conflict analysis unit configured for determining successively whether a register for executing the ith instruction determined by (1≦i≦K/2) when K is the even number or by (1≦i≦(K+1)/2−1) when K is the odd number of the K instructions and a register for executing any instruction from the jth determined by ((K/2+1)≦j≦K) when the K is the even number or by (((K+1)/2+1)≦j≦K) when K is the odd number to Kth instructions have conflicts;

an instruction dividing unit configured for dividing the K instructions in the loop into a first combined instruction section, a connection instruction section and a second combined instruction section, wherein there is no resource conflict between instructions in the first combined instruction section and the instructions in the second combined instruction section respectively; and

a program compiler configured for compiling the program, wherein instructions in the first combined instruction section in a cycle N (N=2, 3, . . . M) and instructions in the second combined instruction section in a cycle N−1 are compiled in parallel respectively.

8. A computer system including a memory, an input and output apparatus for a program including a loop, the loop in the program including K instructions (K≧2) and repeating for M times (M≧2), the compiling apparatus comprising:

a resource conflict analysis unit configured for performing resource conflict analysis on the K instructions in the loop, the resource conflict analysis unit comprises:

a functional unit conflict analysis configured for determining successively and respectively whether functional units for executing an ith instruction determined by (1≦i≦K/2) when K is an even number or by (1≦i≦((K+1)/2−1)) when K is an odd number and functional units for executing a jth instruction determined by ((K/2+1)≦j≦K) when K is an even number or by (((K+1)/2+1)≦j≦K) when K is an odd number, in the K instructions, have conflicts; and

a register conflict analysis unit configured for determining successively whether a register for executing the ith instruction determined by (1≦i≦K/2) when K is the even number or by (1≦i≦(K+1)/2-1) when K is the odd number of the K instructions and a register for executing any instruction from the jth determined by ((K/2+1)≦j≦K) when the K is the even number or by (((K+1)/2+1)≦j≦K) when K is the odd number to Kth instructions have conflicts;

an instruction dividing unit configured for dividing the K instructions in the loop into a first combined instruction section, a connection instruction section and a second combined instruction section, wherein there is no resource conflict between instructions in the first combined instruction section and the instructions in the second combined instruction section respectively; and

a program compiler configured for compiling the program, wherein instructions in the first combined instruction section in a cycle N (N=2, 3, . . . M) and instructions in the second combined instruction section in a cycle N−1 are compiled in parallel respectively.