IP Library Granted Patent US 7,619,255
Granted Patent B2
US 7,619,255 · App. 11/723,600 · Granted Nov 17, 2009

Layer-stacked wiring and method for manufacturing same and semiconductor device using same and method for manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,619,255
App. No.
11/723,600
Granted
Nov 17, 2009
Kind
B2
Abstract

A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.

Claims (18)

1. A semiconductor device comprising:

a polycrystalline silicon thin film having a source region and a drain region at its both ends, which is formed on an insulating substrate with a frontend insulating film interposed between said polycrystalline silicon thin film and said insulating substrate; and

a gate electrode formed on said polycrystalline silicon thin film with a gate insulating film interposed between said gate electrode and said polycrystalline silicon thin film, wherein said gate electrode comprises a layer-stacked wiring comprising:

a microcrystalline silicon thin film; and

a metal thin film formed on said microcrystalline silicon thin film,

wherein crystal grains making up a crystal structure of said microcrystalline silicon thin film, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of said microcrystalline silicon thin film amount to 15% or less of total number of said crystal grains.

2. A semiconductor device comprising:

a polycrystalline silicon thin film having a source region and a drain region at its both ends, which is formed on an insulating substrate with a frontend insulating film interposed between said polycrystalline silicon thin film and said insulating substrate; and

a gate electrode formed on said polycrystalline silicon thin film with a gate insulating film interposed between said gate electrode and said polycrystalline silicon thin film, wherein said gate electrode comprises a layer-stacked wiring comprising:

a microcrystalline silicon thin film; and

a metal thin film formed on said microcrystalline silicon thin film,

wherein crystal grains making up a crystal structure of said microcrystalline silicon thin film, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of said microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains.

3. A method for manufacturing a semiconductor device comprising:

a process of forming an amorphous silicon thin film on an insulating substrate with a frontend insulating film interposed between said amorphous silicon thin film and said insulating substrate;

a process of crystallizing said amorphous silicon thin film to form a polycrystalline silicon thin film by performing a laser annealing process on said amorphous silicon thin film;

a process of forming, after making said polycrystalline silicon thin film have an island structure, a layer-stacked film comprising a microcrystalline silicon thin film and a metal thin film which are stacked sequentially on a gate insulating film; and

a process of performing patterning on said layer-stacked film to form a gate electrode having a desired shape;

wherein, as said microcrystalline silicon thin film, a thin film is used whose crystal grains, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of said thin film amount to 15% or less of total number of crystal grains making up said thin film or whose crystal grains, each having a length of said thin film in a direction of a film thickness being 50% or less of a film thickness of said thin film amount to 85% or more of the total number of crystal grains making up said thin film.

Assignments (3)
CHANGE OF NAME Recorded Nov 8, 2011
From: NEC LCD TECHNOLOGIES, LTD.
To: NLT TECHNOLOGIES, LTD.
Reel/Frame 027189/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2010
From: NEC CORPORATION
To: NEC LCD TECHNOLOGIES, LTD.
Reel/Frame 024495/0216 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2007
From: TANAKA, JUN; KANOH, HIROSHI
To: NEC CORPORATION; NEC LCD TECHNOLOGIES, LTD.
Reel/Frame 019135/0344 →