Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof
A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.
1. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a gate starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit,
said controlled delay circuit further comprises an input switching circuit having a plurality of switching units each corresponding to a respective one of said gate units, said input switching circuit being disposed between said delay gate array and said data storage and gate specifying circuit, said input switching circuit supplying the input signal to said delay gate array.
2. A controlled delay circuit as claimed in claim 1 , wherein each of said gate units receives the output of the preceding gate unit, the input signal, and the output of a corresponding unit circuit of said data storage and gate specifying circuit.
3. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a gate starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit; and
said controlled delay circuit further comprises an input switching circuit for supplying the input signal to one of said gate units according to the data stored in said data storage and gate specifying circuit.
4. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a delay starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit;
said controlled delay circuit further comprises an input switching circuit for supplying the input signal to one of said gate units according to the data stored in said data storage and gate specifying circuit; and
each of said gate units receives the output of the preceding gate unit and the output of a corresponding switching unit of said switching circuit.
5. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a delay starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit;
said controlled delay circuit further comprises an input switching circuit for supplying the input signal to one of said gate units according to the data stored in said data storage and gate specifying circuit;
each of said gate units receives the output of the preceding gate unit and the output of a corresponding switching unit of said switching circuit; and
each of said switching units is switched according to the output of a corresponding unit circuit of said data storage and gate specifying circuit.
6. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a gate starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit; and
said data storage and gate specifying circuit is a register circuit that receives a write signal and an address signal to specify one of said gate units that starts to delay the input signal.
7. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a delay starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit;
said data storage and gate specifying circuit is a register circuit that receives a write signal and an address signal to specify one of said gate units that starts to delay the input signal; and
said register circuit is reset in response to a reset signal.
8. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a delay starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit;
said data storage and gate specifying circuit is a shift register circuit that receives a shift signal to specify one of said gate units that starts to delay the input signal; and
said controlled delay circuit further comprises an input switching circuit having a plurality of switching units each corresponding to a respective one of said gate units, said input switching circuit being disposed between said delay gate array and said data storage and gate specifying circuit, said input switching circuit supplying the input signal to said delay gate array.
9. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a delay starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit;
said data storage and gate specifying circuit is a shift register circuit that receives a shift signal to specify one of said gate units that starts to delay the input signal; and
said shift register circuit is reset is response to a reset signal.
10. A controlled delay circuit for adding a given delay to an input signal and providing a delayed output signal, comprising:
a data storage and gate specifying circuit having a data storage function; and
a delay gate array having cascaded gate units in series,
wherein said data storage and gate specifying circuit specifies one of said gate units as a delay starting portion in said delay gate array, according to the data stored in said data storage and gate specifying circuit,
wherein said controlled delay circuit further comprises:
a comparator for comparing the output signal of said delay gate array with a reference signal; and
a controller for feed-back controlling, in response to the output of said comparator, signals supplied to said data storage and gate specifying circuit to specify one of said gate units that starts to delay the input signal.
11. A control signal generator for generating a control signal whose period is determined according to the period of an input signal, comprising:
a first gate array having cascaded first gate units to receive the input signal;
a second gate array having cascaded second gate units to receive the output of said first gate array;
a comparator for comparing the output of said second gate array with the input signal; and
a gate specifying circuit for specifying, according to the output of said comparator, one of said first gate units that starts to delay the input signal as well as one of said second gate units that starts to delay the output of said first gate array.
12. A control signal generator as claimed in claim 11 , wherein said control signal generator provides an output signal whose frequency is twice as large as that of the input signal.
13. A control signal generator as claimed in claim 12 , wherein said control signal generator further comprises an output logic circuit for providing a result of logical operation of the output of said first gate array and the output of said second gate array.
14. A control signal generator as claimed in claim 12 , wherein said control signal generator further comprises an output logic circuit for providing a result of logical operation of the input signal and the output of said first gate array.