Charge-trap type non-volatile memory devices and related methods

1. A non-volatile memory device comprising:

a semiconductor substrate;

a device isolation layer on the semiconductor substrate separating first and second active regions of the semiconductor substrate on opposite sides of the device isolation layer;

first and second tunnel insulating patterns on the first and second active regions;

first and second charge-trap patterns on the respective first and second tunnel insulating patterns wherein portions of the device isolation layer between the first and second charge-trap patterns are free of the first and second charge-trap patterns;

a first blocking insulating layer on the first and second charge-trap patterns and on portions of the device isolation layer between the first and second charge-trap patterns so that the first and second charge-trap patterns are between the first blocking insulating layer and the first and second tunnel insulating patterns;

a word line on the first blocking insulating layer so that the first blocking insulating layer is between the wordline and the first and second charge-trap patterns and between the word line and the device isolation layer;

third and fourth tunnel insulating patterns on the first and second active regions spaced apart from the first and second tunnel insulating patterns, wherein each of the first, second, third, and fourth tunnel insulating patterns comprises a first insulating material having a first dielectric constant;

a second blocking insulating layer directly on the third and fourth tunnel insulating patterns and on portions of the device isolation layer between the third and fourth tunnel insulating patterns, wherein the second blocking insulating layer is spaced apart from the first blocking insulating layer, and wherein each of the first and second blocking insulating layers comprises a second insulating material having a second dielectric constant, and wherein the first and second dielectric constants are different; and

a gate electrode line on the second blocking insulating layer so that the second blocking insulating layer is between the gate electrode line and the third and fourth tunnel insulating patterns and between the gate electrode line and the device isolation layer, wherein a separation between the selection line and the first and second active regions of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.

2. A non-volatile memory device according to claim 1 , further comprising:

spacers on sidewalls of the gate electrode line, wherein the first and second tunnel insulating patterns are between the spacers and the semiconductor substrate in a direction perpendicular with respect to a surface of the semiconductor substrate, and wherein the second blocking insulating layer is between the spacers and the semiconductor substrate in the direction perpendicular with respect to the surface of the semiconductor substrate.

3. A non-volatile memory device comprising:

a semiconductor substrate;

a device isolation layer on the semiconductor substrate separating first and second active regions of the semiconductor substrate on opposite sides of the device isolation layer;

first and second tunnel insulating patterns on the first and second active regions;

first and second charge-trap patterns on the respective first and second tunnel insulating patterns wherein portions of the device isolation layer between the first and second charge-trap patterns are free of the first and second charge-trap patterns;

a first blocking insulating layer on the first and second charge trap patterns and on portions of the device isolation layer between the first and second charge trap patterns;

a word line on the first blocking insulating layer the first and second charge-trap patterns and on portions of the device isolation layer between the first and second charge-trap patterns wherein the blocking insulating layer is between the word line and the first and second charge-trap patterns and between the word line and the device isolation layer;

a third tunnel insulating pattern on the semiconductor substrate spaced apart from the first and second tunnel insulating patterns, wherein each of the first, second, and third tunnel insulating patterns comprises a first insulating material having a first dielectric constant;

a second blocking insulating layer directly on the third tunnel insulating pattern, wherein the second blocking insulating layer is spaced apart from the first blocking insulating layer, wherein each of the first and second blocking insulating layers comprises a second insulating material having a second dielectric constant, and wherein the first and second dielectric constants are different; and

a gate electrode line on the second blocking insulating layer so that the second blocking insulating layer is between the gate electrode line and the third tunnel insulating pattern.

4. A non-volatile memory device according to claim 3 wherein the first dielectric constant is less than the second dielectric constant.

5. A non-volatile memory device according to claim 3 wherein each of the first and second charge-trap patterns has a respective sidewall directly adjacent respective sidewalls of the device isolation layer.

6. A non-volatile memory device according to claim 3 wherein the word line comprises a material having a work function higher than that of polysilicon.

7. A non-volatile memory device according to claim 3 wherein the word line comprises a material including metal.

8. A non-volatile memory device according to claim 3 wherein a surface of the device isolation layer opposite the semiconductor substrate extends at least as far from the semiconductor substrate as surfaces of the charge-trap patterns opposite the semiconductor substrate.

9. A non-volatile memory device according to claim 3 wherein the semiconductor substrate comprises a cell array region and a peripheral circuit region, wherein the gate electrode line comprises a peripheral circuit gate electrode on the peripheral circuit region of the semiconductor substrate, and wherein the word line is on the cell array region of the semiconductor substrate, wherein a separation between the peripheral circuit gate electrode and the peripheral circuit region of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.

10. A non-volatile memory device according to claim 9 further comprising:

spacers on sidewalls of the peripheral circuit gate electrode, wherein the third tunnel insulating pattern and the second blocking insulating layer are between the spacers and the semiconductor substrate in a direction parallel with respect to a surface of the semiconductor substrate.

11. A non-volatile memory device according to claim 3 , further comprising:

spacers on sidewalls of the word line, wherein the first and second charge-trap patterns are between the spacers and the semiconductor substrate in a direction perpendicular with respect to a surface of the semiconductor substrate.

12. A non-volatile memory device according to claim 3 wherein the each of the first and second blocking insulating layers comprises a layer including hafnium oxide, aluminum oxide, hafnium aluminum oxide, and/or zirconium oxide.

13. A non-volatile memory device according to claim 3 wherein the third tunnel insulating pattern is on the first active region of the semiconductor substrate, the non-volatile memory device further comprising:

a fourth tunnel insulating pattern on the second active region spaced apart from the first and second tunnel insulating patterns, wherein the second blocking insulating layer is directly on the third and fourth tunnel insulating patterns and on portions of the device isolation layer between the third and fourth tunnel insulating patterns, and wherein the second blocking insulating layer between the gate electrode line and the third and fourth tunnel insulating patterns and the semiconductor substrate and between the gate electrode line and the device isolation layer wherein a separation between the gate electrode line and the first and second active regions of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.

14. A non-volatile memory device according to claim 13 , further comprising:

spacers on sidewalls of the gate electrode line, wherein the third and fourth tunnel insulating patterns are between the spacers and the semiconductor substrate in a direction perpendicular with respect to a surface of the semiconductor substrate, and wherein the second blocking insulating layer is between the spacers and the semiconductor substrate in the direction perpendicular with respect to the surface of the semiconductor substrate.

15. A non-volatile memory device according to claim 3 wherein the third tunnel insulating pattern is on the first active region of the semiconductor substrate, the memory device further comprising:

a fourth tunnel insulating pattern on the second active region spaced apart from the first and second charge-trap patterns wherein the second blocking insulating layer is between the gate electrode line and the third and fourth tunnel insulating patterns and between the gate electrode line and portions of the device isolation layer between the third and fourth tunnel insulating patterns, and wherein a separation between the gate electrode line and the first and second active regions of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.

16. A method of forming a non-volatile memory device, the method comprising:

forming a device isolation layer on portions of a semiconductor substrate separating first and second active regions of the semiconductor substrate on opposite sides of the device isolation layer;

forming first and second tunnel insulating patterns on the first and second active regions of the semiconductor substrate;

forming first and second charge-trap patterns on the respective first and second tunnel insulating patterns wherein portions of the device isolation layer between the first and second charge-trap patterns are free of the first and second charge-trap patterns;

forming a first blocking insulating layer on the first and second charge-trap patterns and on portions of the device isolation layer between the first and second charge-trap patterns so that the first and second charge-trap patterns are between the first blocking insulating layer and the first and second tunnel insulating patterns;

forming a word line on the first blocking insulating layer so that the first blocking insulating layer is between the word line and the first and second charge-trap patterns and between the word line and the device isolation layer

forming third and fourth tunnel insulating patterns on the first and second active regions spaced apart from the first and second tunnel insulating patterns, wherein the first, second, third, and fourth tunnel insulating patterns are formed simultaneously;

forming a second blocking insulating layer directly on the third and fourth tunnel insulating patterns and on portions of the device isolation layer between the third and fourth tunnel insulating patterns, wherein the second blocking insulating layer is spaced apart from the first blocking insulating layer, wherein the first and second blocking insulating layers are formed simultaneously; and

forming a gate electrode line on the second blocking insulating layer so that the second blocking insulating layer is between the gate electrode line and the third and fourth tunnel insulating patterns and between the gate electrode line and the device isolation layer, wherein a separation between the selection line and the first and second active regions of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.

17. A method of forming a non-volatile memory device, the method comprising:

forming a device isolation layer on portions of a semiconductor substrate separating first and second active regions of the semiconductor substrate on opposite sides of the device isolation layer;

forming first and second tunnel insulating patterns on the first and second active regions of the semiconductor substrate;

forming first and second charge-trap patterns on the respective first and second tunnel insulating patterns wherein portions of the device isolation layer between the first and second charge-trap patterns are free of the first and second charge-trap patterns;

forming a first blocking insulating layer on the first and second charge-trap patterns and on the device isolation layer;

forming a word line on the first blocking insulating layer so that the first blocking insulating layer is between the word line and the first and second charge-trap patterns and between the word line and the device isolation layer;

forming a third tunnel insulating pattern on the semiconductor substrate spaced apart from the first and second tunnel insulating patterns, wherein the first, second, and third tunnel insulating patterns are formed simultaneously;

forming a second blocking insulating layer directly on the third tunnel insulating pattern, wherein the second blocking insulating layer is spaced apart from the first blocking insulating layer, and wherein the first and second blocking insulating layers are formed simultaneously; and

forming a gate electrode line on the second blocking insulating layer so that the second blocking insulating layer is between the gate electrode line and the third tunnel insulating pattern.

18. A method according to claim 17 wherein each of the first, second, and third tunnel insulating layers comprises a layer of a first insulating material having a first dielectric constant, wherein each of the first and second blocking insulating layers comprises a layer of a second insulating material having a second dielectric constant, and wherein the first dielectric constant is less than the second dielectric constant.

19. A method according to claim 17 wherein each of the first and second charge-trap patterns has a respective sidewall directly adjacent respective sidewalls of the device isolation layer.

20. A method according to claim 17 wherein the word line comprises a material having a work function higher than that of polysilicon.

21. A method according to claim 17 wherein the word line comprises a material including a metal.

22. A method according to claim 17 wherein a surface of the device isolation layer opposite the semiconductor substrate extends at least as far from the semiconductor substrate as surfaces of the charge-trap patterns opposite the semiconductor substrate.

23. A method according to claim 17 wherein the semiconductor substrate comprises a cell array region and a peripheral circuit region, wherein the word line is on the cell array region, wherein the gate electrode line comprises a peripheral circuit gate electrode on the peripheral circuit region, and wherein a separation between the peripheral circuit gate electrode and the peripheral circuit region of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.

24. A method according to claim 17 , further comprising:

forming spacers on sidewalls of the word line, wherein the first and second charge-trap patterns are between the spacers and the semiconductor substrate in a direction perpendicular with respect to a surface of the semiconductor substrate.

25. A method according to claim 17 wherein each of the first and second blocking insulating layers comprises a layer including hafnium oxide, aluminum oxide, hafnium aluminum oxide, and/or zirconium oxide.

26. A method according to claim 17 wherein the third tunnel insulating pattern is on the first active region of the semiconductor substrate, the method further comprising:

forming a fourth tunnel insulating pattern on the second active regions spaced apart from the first and second tunnel insulating patterns, wherein forming the second blocking insulating layer comprises forming the second blocking insulating layer directly on the third and fourth tunnel insulating patterns and on portions of the device isolation layer between the third and fourth tunnel insulating patterns, and wherein the second blocking insulating layer is between the gate electrode line and the third and fourth tunnel insulating patterns and the semiconductor substrate and between gate electrode line and the device isolation layer wherein a separation between the gate electrode line and the first and second active regions of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.

27. A method according to claim 17 wherein the third tunnel insulating pattern is on the first active region of the semiconductor substrate, the method further comprising:

forming a fourth tunnel insulation pattern on the second active region spaced apart from the first and second charge-trap patterns wherein the second blocking insulating layer is between the gate electrode line and the third and fourth tunnel insulating patterns and between the gate electrode line and the device isolation layer, wherein a separation between the gate electrode line and the first and second active regions of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.