Systems for forcing an update block to remain sequential
A non-volatile memory system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. The processor is configured to provide a sequential update block, preexisting data associated with the sequential update block, and an option to convert the sequential update block to a chaotic update block. The processor is further configured to receive a write command to write data following a previous write command, where the write command and the previous write command have a discontinuity in logical addresses. If a logical address of the write command is different from the logical addresses of the preexisting data, data are written to the sequential update block. However, if the logical address of the write command matches one of the logical addresses of the preexisting data, then the sequential update block is converted to a chaotic update block.
1 . A non-volatile memory storage system, comprising:
a non-volatile memory cell array; and
a processor in communication with the non-volatile memory cell array, the processor being configured to
provide a sequential update block and preexisting data associated with the sequential update block,
provide an option to convert the sequential update block to a chaotic update block,
receive a write command to write data following a previous write command, the write command and the previous write command having a discontinuity in logical addresses,
write the data to the sequential update block if a logical address of the write command is different from logical addresses of the preexisting data, and
convert the sequential update block to a chaotic update block if the logical address of the write command matches one of the logical addresses of the preexisting data.
2 . The non-volatile memory storage system of claim 1 , wherein the processor is further configured to write the data to the chaotic update block if the logical address of the write command matches one of the logical addresses of the preexisting data.
3 . The non-volatile memory storage system of claim 1 , wherein the logical address of the write command matches one of the logical addresses of the preexisting data in a backward address transition.
4 . A non-volatile memory storage system, comprising:
a non-volatile memory cell array; and
a processor in communication with the non-volatile memory cell array, the processor being configured to
provide a sequential update block and preexisting data associated with the sequential update block,
provide an option to convert the sequential update block to a chaotic update block,
receive a write command to write data following a previous write command, the write command and the previous write command having a discontinuity in logical addresses,
convert the sequential update block to a chaotic update block if the logical address of the write command matches one of the logical addresses of the preexisting data, and
write the data to the chaotic update block.
5 . The non-volatile memory storage system of claim 4 , wherein the processor is further configured to write the data to the sequential update block if a logical address of the write command is different from logical addresses of the preexisting data.
6 . The non-volatile memory storage system of claim 4 , wherein the logical address of the write command matches one of the logical addresses of the preexisting data in a backward address transition.
7 . The non-volatile memory storage system of claim 4 , wherein the discontinuity in logical addresses defines a gap between a logical address of the write command and a logical address of the previous write command.
8 . The non-volatile memory storage system of claim 7 , wherein the processor is further configured to:
provide a block associated with the sequential update block, the block comprising valid data associated with the gap and invalid data; and
copy the valid data associated with the gap from the block to the sequential update block.