System and method to control one time programmable memory
View Patent ↗Systems and methods to control one time programmable (OTP) memory are included. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data.
1. A method for an integrated circuit to modify a capability of the integrated circuit, the method comprising:
disabling at least one capability in the integrated circuit by setting at least one bit in a one-time-programmable (OTP) memory bank in the integrated circuit; and
copying bits of the OTP memory bank to at least one register that is accessible by a processor when the OTP memory bank is not read-enabled.
2. The method of claim 1 further comprising setting a corresponding lock bit when the at least one bit has been written once to the OTP memory bank.
3. The method of claim 1 further comprising setting the at least one bit after the integrated circuit has been shipped from a manufacturer.
4. The method of claim 1 wherein the integrated circuit further comprises multiple OTP memory banks and wherein at least one of the multiple OTP memory banks is dedicated to store a cryptographic key.
5. The method of claim 1 further comprising allowing the at least one bit to be set until a lock bit is set.
6. The method of claim 1 further comprising:
setting a clock of the OTP memory bank to a frequency;
raising a first voltage of the OTP memory bank to a first level;
determining if the OTP memory bank is in a read state; and
setting the at least one bit in the OTP memory bank when the clock is at the frequency, the first voltage is at the first level, and the OTP memory bank is not in a read state.
7. The method of claim 6 wherein the first level comprises a voltage level greater than an operating voltage of the OTP memory bank, the operating voltage for reading data from the OTP memory bank.
8. The method of claim 1 further comprising:
storing a memory address for a write operation in a first register;
storing a copy of the memory address in a second register; and
preventing modification of the copy until a write operation is complete.
9. The method of claim 1 , wherein the at least one register is writeable until a first lock bit in the OTP memory bank is set.
10. The method of claim 9 , wherein the first lock bit is writeable until a second lock bit in a lock register is set.
11. A computer readable medium having instructions to cause a processor to perform a method comprising:
determining a functionality for a hardware capability bus in an integrated circuit;
disabling the functionality in the integrated circuit by setting at least one bit in a one-time-programmable (OTP) memory bank in the integrated circuit; and
copying bits of the OTP memory bank to registers that are accessible by the processor when the OTP memory bank is not read-enabled.
12. The computer readable medium of claim 11 wherein the method further comprises:
determining when a lock bit has been set; and
preventing setting the at least one bit in the OTP memory bank when the lock bit has been set.
13. The computer readable medium of claim 11 wherein the method further comprises:
setting a clock of the OTP memory bank to a frequency;
raising a first voltage of the OTP memory bank to a first level;
determining if the OTP memory bank is in a read state; and
setting the at least one bit in the OTP memory bank when the clock is at the frequency, the first voltage is at the first level, and the OTP memory bank is not in a read state.
14. The computer readable medium of claim 11 wherein the method further comprises:
storing a memory address for a write operation in a first register;
storing a copy of the memory address in a second register; and
preventing modification of the copy until a write operation is complete.
15. The computer readable medium of claim 11 , wherein the instructions cause the processor to set an error bit when a second read operation on the OTP memory bank is attempted while a first read or write operation upon the OTP memory bank is being performed.