Multiple-gate MOS transistor and a method of manufacturing the same
View Patent ↗Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.
1. A multiple-gate metal oxide semiconductor (MOS) transistor, comprising:
a substrate formed of an insulating layer thereon;
a single-crystal silicon pattern formed on the insulating layer and providing source and drain regions, a channel region formed between the source and drain regions, and an expansion region interconnecting the source and drain regions with the channel region;
a gate insulating layer formed on the single-crystal silicon pattern of the channel region; and
a gate electrode formed on the gate insulating layer of the channel region,
wherein the single-crystal silicon pattern of the channel region has an upper portion defining a smooth curve; and
a height and width of the single-crystal silicon pattern of the expansion region is gradually increased toward the source and drain regions.
2. The multiple-gate MOS transistor as recited in claim 1 , wherein the single-crystal silicon pattern of the source and drain regions has a thickness larger than that of the single-crystal silicon pattern of the channel region and the expansion region.
3. The multiple-gate MOS transistor as recited in claim 1 , wherein the gate electrode is formed to partially overlap the expansion region.
4. The multiple-gate MOS transistor as recited in claim 1 , wherein the gate electrode is formed to extend to an upper portion of the insulating layer.