Processing apparatus with memories coupled to respective processors
View Patent ↗In a processing apparatus, a plurality of processors which perform different kinds of processing is integrated on a first semiconductor substrate. A plurality of memories to be managed by the plurality of processors integrated on the first semiconductor substrate is integrated on a second semiconductor substrate. The plurality of processors integrated on the first semiconductor substrate includes respective separate memory controllers which control the memories to be managed that are integrated on the second semiconductor substrate. The semiconductor substrates are manufactured using different semiconductor manufacturing processes, and micro bumps are formed on their respective surfaces. The semiconductor substrates are stacked together in the thickness direction, and are connected to each other through the micro bumps.
1. A processing apparatus comprising:
a first semiconductor substrate on which a plurality of processors configured to perform different types of processing from one another are formed; and
a second semiconductor substrate on which a plurality of memories are formed, each of the memories coupled to a respective one of the plurality of processors; and
micro bumps formed on the surfaces of the first and second semiconductor substrates,
wherein the plurality of processors includes respective separate memory controllers coupled to the memories,
wherein the first and second semiconductor substrates are stacked together in a thickness direction, and coupled to each other through the micro bumps,
wherein the second semiconductor substrate is a substrate manufactured by a semiconductor process having a coarser pitch than the pitch of the first semiconductor substrate.
2. The processing apparatus according to claim 1 , wherein the plurality of processors and the respective plurality of memories are arranged so that the respective micro bumps thereof at least partially overlap each other.
3. A processing apparatus comprising:
an arithmetic processor configured to perform general-purpose processing;
a memory coupled to the arithmetic processor;
a plurality of application-specific processors configured to perform application-specific types of processing;
an image processor configured to perform processing of images;
an image memory coupled to the image processor; and
application-specific memories coupled to the plurality of application-specific processors,
wherein the arithmetic processor and the application-specific processors excluding the image processor are formed on a first semiconductor substrate, and
wherein the memory coupled to the arithmetic processor and the application-specific memories coupled to the respective application-specific processors excluding the image processor are formed on a second semiconductor substrate.
4. The processing apparatus according to claim 3 , wherein the image processor and the image memory are formed on a third semiconductor substrate.
5. The processing apparatus according to claim 3 , wherein the second semiconductor substrate is a substrate manufactured by a semiconductor process having a coarser pitch than the pitch of the first semiconductor substrate.