Conductive container structures having a dielectric cap
Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
1 . A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
exposing a portion of the substrate through an insulating layer on the substrate;
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer that is about a top of the insulating layer;
removing the conductive layer and the fill layer to a level below the top of the insulating layer;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a first dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the first dielectric layer from the insulating layer and the fill layer;
a second dielectric layer on the bottom plate and the dielectric cap, wherein the second dielectric layer is formed by a method comprising:
exposing the sidewalls of the bottom plate; and
forming a dielectric layer on the bottom plate;
a cell plate on the second dielectric layer, wherein the second dielectric layer is interposed between the cell plate and the bottom plate.
2 . The semiconductor die of claim 1 , wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon.
3 . The semiconductor die of claim 1 , wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides.
4 . The semiconductor die of claim 1 , wherein the dielectric cap is annealed.
5 . The semiconductor die of claim 1 , wherein a shape of the bottom plate is selected from the group consisting of: a cylindrical shape; an oval shape; and an irregular shape.
6 . The semiconductor die of claim 1 , wherein the dielectric cap forms a part of the second dielectric layer.
7 . The semiconductor die of claim 1 , wherein the dielectric cap protects the bottom plate from container-to-container bridging of conductive debris resulting from exposing the sidewalls of the bottom plate.
8 . The semiconductor die of claim 2 , wherein the silicon material is conductively doped.
9 . The semiconductor die of claim 4 , wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds.
10 . A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
exposing a portion of the substrate through an insulating layer on the substrate;
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer that is about a top of the insulating layer;
removing the conductive layer and the fill layer to a level below the top of the insulating layer;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a first dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the first dielectric layer from the insulating layer and the fill layer;
a second dielectric layer on the bottom plate and the dielectric cap, wherein the second dielectric layer is formed by a method comprising:
exposing the sidewalls of the bottom plate; and
forming a dielectric layer on the bottom plate;
a cell plate on the second dielectric layer,
wherein the dielectric cap protects the bottom plate from container-to-container bridging of conductive debris resulting from exposing the sidewalls of the bottom plate.
11 . The semiconductor die of claim 1 , wherein the second dielectric layer is interposed between the cell plate and the bottom plate.
12 . The semiconductor die of claim 10 , wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon.
13 . The semiconductor die of claim 10 , wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides.
14 . The semiconductor die of claim 10 , wherein the dielectric cap is annealed.
15 . The semiconductor die of claim 10 , wherein a shape of the bottom plate is selected from the group consisting of: a cylindrical shape; an oval shape; and an irregular shape.
16 . The semiconductor die of claim 10 , wherein the dielectric cap forms a part of the second dielectric layer.
17 . The semiconductor die of claim 12 , wherein the silicon material is conductively doped.
18 . The semiconductor die of claim 14 , wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds.
19 . A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
exposing a portion of the substrate through an insulating layer on the substrate,
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer that is about a top of the insulating layer; and
removing the conductive layer to level below the top of the insulating layer;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a first dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the first dielectric layer from the insulating layer and the fill layer;
a second dielectric layer on the bottom plate and the dielectric cap, wherein the second dielectric layer is formed by a method comprising:
exposing the sidewalls of the bottom plate; and
forming a dielectric layer on the bottom plate;
a cell plate on the second dielectric layer, wherein the second dielectric layer is interposed between the cell plate and the bottom plate.
20 . The semiconductor die of claim 19 , wherein the dielectric cap protects the bottom plate from container-to-container bridging of conductive debris resulting from exposing the sidewalls of the bottom plate.
21 . The semiconductor die of claim 19 , wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon.
22 . The semiconductor die of claim 19 , wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides.
23 . The semiconductor die of claim 19 , wherein the dielectric cap is annealed.
24 . The semiconductor die of claim 19 , wherein a shape of the bottom plate is selected from the group consisting of: a cylindrical shape; an oval shape; and an irregular shape.
25 . The semiconductor die of claim 19 , wherein the dielectric cap forms a part of the dielectric layer.
26 . The semiconductor die of claim 21 , wherein the silicon material is conductively doped.
27 . The semiconductor die of claim 23 , wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds.
28 . A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
exposing a portion of the substrate through an insulating layer on the substrate,
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer that is about a top of the insulating layer; and
removing the conductive layer to level below the top of the insulating layer;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a first dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the first dielectric layer from the insulating layer and the fill layer;
a second dielectric layer on the bottom plate and the dielectric cap, wherein the second dielectric layer is formed by a method comprising:
exposing the sidewalls of the bottom plate; and
forming a dielectric layer on the bottom plate;
a cell plate on the second dielectric layer;
wherein the dielectric cap protects the bottom plate from container-to-container bridging of conductive debris resulting from exposing the sidewalls of the bottom plate.
29 . The semiconductor die of claim 28 , wherein the second dielectric layer is interposed between the cell plate and the bottom plate.
30 . The semiconductor die of claim 28 , wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon.
31 . The semiconductor die of claim 28 , wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides.
32 . The semiconductor die of claim 28 , wherein the dielectric cap is annealed.
33 . The semiconductor die of claim 28 , wherein a shape of the bottom plate is selected from the group consisting of: a cylindrical shape; an oval shape; and an irregular shape.
34 . The semiconductor die of claim 28 , wherein the dielectric cap forms a part of the dielectric layer.
35 . The semiconductor die of claim 30 , wherein the silicon material is conductively doped.
36 . The semiconductor die of claim 32 , wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds.
37 . A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom;
a dielectric cap on a top of the sidewalls to protect the bottom plate from container-to-container bridging of conductive debris;
a dielectric layer on the bottom plate and the dielectric cap; and
a cell plate on the dielectric layer.
38 . The semiconductor die of claim 37 , wherein the dielectric layer is interposed between the cell plate and the bottom plate.
39 . The semiconductor die of claim 37 , wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon.
40 . The semiconductor die of claim 37 , wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides.
41 . The semiconductor die of claim 37 , wherein the dielectric cap is annealed.
42 . The semiconductor die of claim 37 , wherein a shape of the bottom plate is selected from the group consisting of: a cylindrical shape; an oval shape; and an irregular shape.
43 . The semiconductor die of claim 37 , wherein the dielectric cap forms a part of the dielectric layer.
44 . The semiconductor die of claim 39 , wherein the silicon material is conductively doped.
45 . The semiconductor die of claim 41 , wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds.