Reduction of cache flush time using a dirty line limiter
The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit.
1. A method for reducing cache flush time of a cache connected to a main memory of a computer system by a system interconnect, comprising:
setting a capacity of a dirty line directory (DLD) residing on a first side of the system interconnect, wherein the capacity defines a maximum number of directory entries in the DLD, and wherein the DLD stores only directory entries corresponding to dirty lines in the cache, wherein the main memory resides on the first side of the system interconnect, and wherein the cache resides on a second side of the system interconnect;
identifying a first modification to the cache;
populating, in response to the first modification, a directory entry of a plurality of directory entries in the DLD, wherein the directory entry comprises an address field and a processor field, and wherein the DLD is populated to the capacity after populating the directory entry;
identifying a second modification to the cache after the DLD is populated to the capacity;
de-populating a pre-determined number of the plurality of directory entries in response to identifying the second modification and the DLD being populated to the capacity; and
sending, by the DLD and in response to de-populating the pre-determined number of the plurality of directory entries, a snoop request to the cache over the system interconnect to initiate a write-back from the cache to the main memory.
2. The method of claim 1 , wherein the capacity is set to 10 percent of the cache being modified.
3. The method of claim 1 , wherein the DLD comprises a set-associative array.
4. The method of claim 1 , wherein the at least one populated directory entry is indicated by a flag.
5. The method of claim 1 , wherein the capacity is set based on a system performance statistic.
6. The method of claim 1 , further comprising:
changing the capacity based on a system performance statistic.
7. The method of claim 1 , wherein the pre-determined number is determined based on a system performance statistic.
8. The method of claim 1 , further comprising:
changing the pre-determined number based on a system performance statistic.
9. A system comprising:
a processor;
a system interconnect;
a cache residing on a first side of the system interconnect;
a main memory operatively connected to the processor, associated with the cache, and residing on a second side of the system interconnect, wherein the main memory is a primary memory of the system; and
a dirty line directory (DLD) residing on the second side of the system interconnect, storing only directory entries corresponding to dirty lines in the cache, which:
sets a capacity of the DLD, wherein the capacity defines a maximum number of directory entries in the DLD;
identifies a first modification to the cache;
populates, in response to the first modification of the cache, a directory entry of a plurality of directory entries in the DLD, wherein the directory entry comprises an address field and a processor field, and wherein the DLD is populated to the capacity after populating the directory entry;
identifies a second modification to the cache after the DLD is populated to the capacity;
de-populates a pre-determined number of the plurality of directory entries in response to identifying the second modification of the cache and the DLD being populated to the capacity; and
sends, in response to de-populating the pre-determined number of the plurality of directory entries, a snoop request over the system interconnect to initiate a write-back from the cache to the main memory.
10. The system of claim 9 , wherein the capacity is set to 10 percent of the cache being modified.
11. The system of claim 9 , wherein the DLD comprises a set-associative array.
12. The system of claim 9 , wherein the directory entry is indicated by a flag.
13. The system of claim 9 , wherein the capacity is determined based on a system performance statistic.
14. The system of claim 9 , wherein the capacity is dynamically defined based on a system performance statistic.
15. The system of claim 9 , wherein the pre-determined number is based on a system performance statistic.