Apparatus and method for use in computational fluid dynamics
View Patent ↗An apparatus includes a parallel computation unit including an input port and an output port and a one-dimensional computational fluid dynamics model. The input port is configured to sample at a time t 1 a boundary condition signal for the one-dimensional computational fluid dynamics model and the output port is configured to provide an output signal before the boundary condition signal is sampled at a time t 2.
1. An apparatus comprising:
a plurality of parallel computation units configured to implement a one-dimensional computational fluid dynamics model for controlling a physical system, wherein each parallel computation unit comprises a respective plurality of computation units, and wherein each parallel computation unit is associated with a respective node of the one-dimensional computational fluid dynamics model;
wherein the plurality of parallel computation units are configured to implement the one-dimensional computational fluid dynamics model to receive a first sample of a boundary condition signal for the one-dimensional computational fluid dynamics model at a time t 1 , wherein the boundary condition signal represents a first physical variable sampled at a first location in the physical system; and
wherein the plurality of parallel computation units are configured to implement the one-dimensional computational fluid dynamics model to generate an output signal representing the first physical variable at a second location in the physical system, wherein the second location is not sampled in the physical system, and wherein the output signal is usable for controlling the physical system;
wherein the plurality of parallel computation units are configured to implement the one-dimensional computational fluid dynamics model to generate the output signal before a second sample of the boundary condition signal is received at a time t 2 .
2. The apparatus of claim 1 , wherein the difference between the time t 2 and the time t 1 is between ten microseconds and ten milliseconds.
3. The apparatus of claim 1 , wherein the apparatus is implemented as a field programmable gate array that implements the plurality of parallel computation units.
4. The apparatus of claim 1 , wherein the physical system is an engine, wherein the apparatus is implemented as an engine control unit that controls the engine.