IP Library Granted Patent US 7,605,441
Granted Patent B2
US 7,605,441 · App. 11/730,422 · Granted Oct 20, 2009

Semiconductor device

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Quick Facts
Patent No.
US 7,605,441
App. No.
11/730,422
Granted
Oct 20, 2009
Kind
B2
Abstract

A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.

Claims (60)

1. A semiconductor device comprising:

a first semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface;

a Schottky electrode formed on the first surface of the first semiconductor layer; and

an ohmic electrode electrically connected to the second surface of the first semiconductor layer,

wherein the first semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.

2. The device of claim 1 ,

wherein the highly-resistive regions are formed in a distribution of multiple island-like shapes, and

the island-shaped highly-resistive regions are spaced apart from each other by a distance capable of producing, in applying a reverse bias voltage to the first semiconductor layer, a depletion layer with a depth equal to the depth of the highly-resistive region.

3. The device of claim 1 ,

wherein the Schottky electrode is provided so that an edge thereof is positioned on the highly-resistive region.

4. The device of claim 1 ,

wherein the highly-resistive regions are formed by an ion implantation.

5. The device of claim 1 ,

wherein the first semiconductor layer has a plurality of trenches, and

the highly-resistive regions are formed in the plurality of trenches, respectively.

6. The device of claim 5 ,

wherein the highly-resistive regions are made of undoped polysilicon.

7. The device of claim 1 , further comprising a second semiconductor layer which is formed in a portion of the first semiconductor layer located closer to the second surface and which is made of a group-III nitride semiconductor with the same conductivity type as and a different carrier concentration from the first semiconductor layer.

8. The device of claim 1 , further comprising:

an insulating substrate; and

a third semiconductor layer formed over the insulating substrate and made of a group-III nitride semiconductor with a higher carrier concentration than the first semiconductor layer,

wherein the first semiconductor layer is formed over the third semiconductor layer, and

the ohmic electrode is formed in contact with the third semiconductor layer.

9. The device of claim 1 , further comprising a conductive substrate,

wherein the first semiconductor layer is formed over the conductive substrate.

10. The device of claim 9 ,

wherein the conductive substrate is made of one of silicon, silicon carbide, gallium nitride, and gallium arsenide.

11. The device of claim 9 ,

wherein a region of the first semiconductor layer not formed to have a high resistance has a width of 2 μm or smaller.

12. The device of claim 1 ,

wherein the first semiconductor layer has a carrier concentration of 1×10 17 cm −3 or higher.

13. A semiconductor device comprising:

a first semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface;

a Schottky electrode formed on the first surface of the first semiconductor layer; and

an ohmic electrode electrically connected to the second surface of the first semiconductor layer,

wherein the first semiconductor layer has semiconductor regions selectively formed in at least the upper portion thereof and having a different conductivity type from the first semiconductor layer.

14. The device of claim 13 ,

wherein the semiconductor regions are formed in a distribution of multiple island-like shapes, and

the island-shaped semiconductor regions have a distance therebetween and an impurity concentration both capable of producing, in applying a reverse bias voltage to the first semiconductor layer, a depletion layer with a depth equal to the depth of the semiconductor region.

15. The device of claim 13 ,

wherein the Schottky electrode is provided so that an edge thereof is positioned on the semiconductor region.

16. The device of claim 13 ,

wherein the semiconductor regions are formed by an ion implantation.

17. The device of claim 13 ,

wherein the first semiconductor layer has a plurality of trenches, and

the semiconductor regions are formed in the plurality of trenches, respectively.

18. The device of claim 17 ,

wherein the semiconductor regions are made of polysilicon having a different conductivity type from the first semiconductor layer.

19. The device of claim 13 , further comprising a second semiconductor layer which is formed in a portion of the first semiconductor layer located closer to the second surface and which is made of a group-III nitride semiconductor with the same conductivity type as and a different carrier concentration from the first semiconductor layer.

20. The device of claim 13 , further comprising:

an insulating substrate; and

a third semiconductor layer formed over the insulating substrate and made of a group-III nitride semiconductor with a higher carrier concentration than the first semiconductor layer,

wherein the first semiconductor layer is formed over the third semiconductor layer, and

the ohmic electrode is formed in contact with the third semiconductor layer.

21. The device of claim 13 , further comprising a conductive substrate,

wherein the first semiconductor layer is formed over the conductive substrate.

22. The device of claim 21 ,

wherein the conductive substrate is made of one of silicon, silicon carbide, gallium nitride, and gallium arsenide.

23. The device of claim 13 ,

wherein the first semiconductor layer has a carrier concentration of 1×10 17 cm −3 or higher.

Assignments (2)
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2007
From: NAKAZAWA, KAZUSHI; UENO, HIROAKI; YANAGIHARA, MANABU; UEMOTO, YASUHIRO; TANAKA, TSUYOSHI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 019765/0579 →