Field effect transistor having reduced contact resistance and method for fabricating the same
View Patent ↗A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of In x Al y Ga 1-y N (wherein 0<x≦1, 0≦y <1 and 0<x+y≦1). A non-alloy source electrode and a non-alloy drain electrode are formed on the capping layer so as to be spaced from each other.
1. A field effect transistor comprising:
a layered structure of nitride semiconductors formed on a substrate and including a capping layer made of a compound represented by a general formula of In x Al y Ga 1-y N (wherein 0<x≦1, 0≦y<1 and 0<x+y≦1);
a non-alloy source electrode and a non-alloy drain electrode formed directly on said capping layer and spaced from each other; and
a gate electrode,
wherein said layered structure of nitride semiconductors includes an electron supplying layer formed under said capping layer,
said capping layer has an opening formed in a region between said source electrode and said drain electrode for exposing said electron supplying layer therein,
said gate electrode is formed on a portion of said electron supplying layer exposed in said opening, and
said gate electrode, said source electrode and said drain electrode are made of the same material.
2. The field effect transistor of claim 1 , further comprising an insulating film formed between said gate electrode and said electron supplying layer.
3. The field effect transistor of claim 1 , wherein said layered structure of nitride semiconductors includes a multilayered film that is formed between said capping layer and said electron supplying layer and includes gallium nitride and aluminum gallium nitride alternately stacked.
4. The field effect transistor of claim 1 , wherein said capping layer includes indium, aluminum and gallium in a ratio which satisfies the lattice-matching condition with gallium nitride.
5. The field effect transistor of claim 4 , wherein a value extracted from a ratio of aluminum in said capping layer divided by a ratio of indium in said capping layer is not smaller than approximately 3.6 and not larger than approximately 4.7.
6. The field effect transistor of claim 1 , wherein each of said source electrode, said drain electrode and said gate electrode is made of a layered structure including at least one of or two or more of aluminum, titanium, molybdenum, copper and palladium.
7. The field effect transistor of claim 1 , wherein each of said source electrode and said drain electrode has contact resistance of approximately 1×10 −4 Ωcm 2 or less.
8. The field effect transistor of claim 1 , wherein said capping layer includes an impurity in a concentration of approximately 1×10 19 cm −3 or more.