Method and system for low power refresh of dynamic random access memories
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.
1 - 39 . (canceled)
40 . A method of operating a DRAM device in either a first relatively higher power mode or a second, relatively higher power mode, comprising:
when operating in the first mode, refreshing rows of memory cells in an array one-row-at-a-time at a first rate;
when operating in the second mode, refreshing rows of memory cells in the array multiple rows-at-a-time at a second rate that is slower than the first rate; and
when switching from operation in the first mode to operation in the second mode, transferring data from each row of the array in which data are stored to at least one other row of memory cells.
41 . The method of claim 40 wherein the act of transferring data from each row of the array in which data are stored to at least one other row of memory cells comprises transferring data from each row of the array in which data are stored to a respective adjacent row of memory cells.
42 . The method of claim 40 wherein the act of transferring data from each row of the array in which data are stored to at least one other row of memory cells comprises:
activating a word line for the row in which data are stored thereby coupling each of the memory cells in the row to one of a pair of respective complimentary digit lines;
sensing the voltage between each of the pairs of complimentary digit lines using a respective sense amplifier that drives the differential voltage between the complimentary digit lines to a predetermined voltage; and
while each of the sense amplifiers is driving the predetermined voltage between the respective pair of complimentary digit lines, activating a respective word line for the at least one other row of memory cells thereby coupling one of the digit lines in each of the pairs of complimentary digit lines to the respective memory cell in the at least one other row of memory cells.
43 . The method of claim 42 wherein the act of activating a word line for the at least one other row of memory cells thereby coupling one of the digit lines in each of the pairs of complimentary digit lines to the respective memory cell in the at least one other row of memory cells comprises activating a word line for a respective adjacent row of memory cells thereby coupling one of the digit lines in each of the pairs of complimentary digit lines to the respective memory cell in the respective adjacent row of memory cells.
44 . The method of claim 40 wherein the act of refreshing rows of memory cells in the array multiple rows-at-a-time comprises simultaneously refreshing adjacent rows of memory cells.
45 . The method of claim 40 wherein the DRAM device includes a pair of complimentary digit lines for each column of the array, and wherein, when operating in the second mode, the act of refreshing rows of memory cells in the array multiple rows-at-a-time comprises simultaneously coupling a memory cell in each column of one row of memory cells to the same digit line to which at least one memory cell in the same column of the at least one other row of memory cells is coupled.
46 . The method of claim 40 wherein the DRAM device includes a pair of complimentary digit lines for each column of the array, and wherein, when operating in the second mode, the act of refreshing rows of memory cells in the array multiple rows-at-a-time comprises simultaneously coupling a memory cell in each column of one row of memory cells to a different digit line from which at least one memory cell in the same column of the at least one other row of memory cells is coupled.