IP Library Granted Patent US 8,968,985
Granted Patent B2
US 8,968,985 · App. 11/731,689 · Granted Mar 3, 2015

Method and system for patterning a mask layer

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Quick Facts
Patent No.
US 8,968,985
App. No.
11/731,689
Granted
Mar 3, 2015
Kind
B2
Abstract

The presently described embodiments use a printing process, e.g. a wax printing technique, to pattern a mask layer (such as a soldermask layer) of, for example, a printed circuit. Substantially all other conventional processes in developing soldermask and exposure processes can be maintained. According to the presently described embodiments, each printed circuit will have a unique pattern that matches uniform and non-uniform runout. In one form, the pattern is comprised of wax single drops having a specified gap to make the process transparent to the current industry practice. Furthermore, the single drops can be used for both large and small areas without any development time differences. In at least one form, the wax pattern and the soldermask in the gap are removed during development.

Claims (33)

1. A method for forming a pattern in a layer of ultraviolet curable material on a printed circuit to expose selected portions of the printed circuit, the method comprising:

determining a mask pattern for a mask to be applied to the layer;

forming the mask based on the mask pattern on the layer, the mask having dense and isolated features;

exposing the layer and the mask to ultraviolet light; and,

developing a pattern in the layer such that the mask, corresponding underlying material of the layer, and dams formed during the exposing under corresponding gaps between the dense features and immediately adjacent the underlying material, are removed during the developing to expose the selected portions of the printed circuit.

2. The method as set forth in claim 1 wherein the ultraviolet curable material layer is a soldermask layer.

3. The method as set forth in claim 1 wherein the mask comprises a continuous outline having dots positioned therein.

4. The method as set forth in claim 1 wherein the forming of the mask comprises printing the mask on a soldermask layer.

5. The method as set forth in claim 4 wherein the printing comprises emitting drops of wax material on the soldermask layer in a half-tone pattern.

6. The method as set forth in claim 5 wherein the half-tone pattern comprises a first outline.

7. The method as set forth in claim 6 wherein the half-tone pattern comprises a second pattern.

8. The method as set forth in claim 4 wherein the printing comprises emitting drops of wax material on the soldermask layer to form circles.

9. The method as set forth in claim 4 wherein the printing comprises emitting drops of wax material on the soldermask layer to form lines.

10. The method as set forth in claim 9 wherein the lines form a grid pattern.

11. The method as set forth in claim 9 wherein the lines form polygons.

12. The method as set forth in claim 1 wherein the dams are removed as a result of limited adhesion to the printed circuit.

13. A method for forming a pattern in a soldermask layer coated on a printed circuit board to expose selected portions of the printed circuit board, the printed circuit board having fiducial marks, the method comprising:

soft baking the soldermask layer on the printed circuit board;

analyzing the fiducial marks on the printed circuit board to determine alignment and orientation of the printed circuit board;

generating a mask pattern to be applied to the soldermask layer using the determined alignment and orientation;

forming the mask pattern on the soldermask layer using wax material, the formed mask pattern having dense and isolated features;

exposing the soldermask layer and wax material to ultraviolet light;

developing a pattern in the soldermask layer such that the wax material, corresponding underlying material of the soldermask layer, and dams formed during the exposing under corresponding gaps between the dense features and immediately adjacent the underlying material, are removed during the developing to expose the selected portions of the printed circuit board; and,

hard baking the patterned soldermask material on the printed circuit board.

14. The method as set forth in claim 13 wherein the forming of the mask pattern comprises printing the mask pattern on the soldermask layer.

15. The method as set forth in claim 14 wherein the printing comprises emitting drops of wax material on the soldermask layer in a half-tone pattern.

16. The method as set forth in claim 15 wherein the half-tone pattern comprises a first outline.

17. The method as set forth in claim 16 wherein the half-tone pattern comprises a second pattern.

18. The method as set forth in claim 14 wherein the printing comprises emitting drops of wax material on the soldermask layer to form nested circles.

19. The method as set forth in claim 14 wherein the printing comprises emitting drops of wax material on the soldermask layer to form lines.

20. The method as set forth in claim 19 wherein the lines form a grid pattern.

21. The method as set forth in claim 19 wherein the lines form nested polygons.

22. The method as set forth in claim 13 wherein the dams are removed as a result of limited adhesion to the printed circuit board.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2025
From: XEROX CORPORATION
To: GENESEE VALLEY INNOVATIONS, LLC
Reel/Frame 073842/0479 →
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2007
From: LIMB, SCOTT JONG HO; SHRADER, ERIC J.; SRINIVASAN, UMA
To: PALO ALTO RESEARCH CENTER INCORPORATED
Reel/Frame 019190/0232 →